A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM. - Makoto Suzuki; Suguru Tachibana; Atsuo Watanabe; Shoji Shukuri; Hisayuki Higuchi; Takahiro Nagano; Katsuhiro Shimohigashi (IEEE J. Solid State Circuits, 1989)

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. - Koichiro Ishibashi; Koichi Takasugi; Kunihiro Komiyaji; Hiroshi Toyoshima; Toshiaki Yamanaka; Akira Fukami; Naotaka Hashimoto; Nagatoshi Ohki; Akihiro Shimizu; Takashi Hashimoto; Takahiro Nagano; Takashi Nishida (IEEE J. Solid State Circuits, 1995)

A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. - Koichiro Ishibashi; Kunihiro Komiyaji; Hiroshi Toyoshima; Masataka Minami; Nagatoshi Ohki; Hiroshi Ishida; Toshiaki Yamanaka; Takahiro Nagano; Takashi Nishida (IEEE J. Solid State Circuits, 1995)

Driving source-line cell architecture for sub-1-V high-speed low-power applications. - Hiroyuki Mizuno; Takahiro Nagano (IEEE J. Solid State Circuits, 1996)