An upper bound on the length of a Hamiltonian walk of a maximal planar graph. - Takao Asano; Takao Nishizeki; Takahiro Watanabe (J. Graph Theory, 1980)

An approximation algorithm for the hamiltonian walk problem on maximal planar graphs. - Takao Nishizeki; Takao Asano; Takahiro Watanabe (Discret. Appl. Math., 1983)

Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis. - Itsuo Takanami; Katsushi Inoue; Takahiro Watanabe; Minoru Oka (Syst. Comput. Jpn., 1993)

Real-Time Gesture Recognition Using Maskable Template Model. - Takahiro Watanabe; Chil-Woo Lee; Akitoshi Tsukamoto; Masahiko Yachida (ICMCS, 1996)

Identifying contents page of documents. - Qin Luo; Takahiro Watanabe; Takeshi Nakayama (ICPR, 1996)

Real-time gesture recognition using KL expansion of image sequence. - Takahiro Watanabe; Masahiko Yachida (IROS, 1997)

Real Time Gesture Recognition Using Eigenspace from Multi Input Image Sequence. - Takahiro Watanabe; Masahiko Yachida (FG, 1998)

Real time recognition of gesture and gesture degree information using multi input image sequences. - Takahiro Watanabe; Masahiko Yachida (ICPR, 1998)

Real-time gesture recognition from dynamic images for construction of any interactive system: Application to a virtual conductor system. - Takahiro Watanabe; Chil-Woo Lee; Masahiko Yachida (Syst. Comput. Jpn., 1998)

Real-time gesture recognition using eigenspace from multi-input imagesequences. - Takahiro Watanabe; Masahiko Yachida (Syst. Comput. Jpn., 1999)

Sealed Bid Mulit-object Auctions with Necessary Bundles and Its Application to Spectrum Auctions. - Tomomi Matsui; Takahiro Watanabe (PRIMA, 2001)

An RFID-based multi-service system for supporting conference events. - Takahiro Watanabe; Sozo Inoue; Hiroto Yasuura; Jun Sasaki; Yasushi Aoki; Kazumi Akimoto (AMT, 2005)

Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament. - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (APCCAS, 2006)

On Authentication between Human and Computer. - Takahiro Watanabe; Yasunobu Nohara; Kensuke Baba; Sozo Inoue; Hiroto Yasuura (PerCom Workshops, 2006)

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair. - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (ISCAS, 2007)

Score Sequence Pair Problems of (r11, r12, r22)-Tournaments - - Determination of Realizability - - . - Masaya Takahashi; Takahiro Watanabe; Takeshi Yoshimura (IEICE Trans. Inf. Syst., 2007)

Generating even triangulations of the projective plane. - Yusuke Suzuki; Takahiro Watanabe (J. Graph Theory, 2007)

A Multiprocessor System for a Small Size Soccer Robot Control System. - Ce Li; Yang Jiang; Zhenyu Wu; Takahiro Watanabe (DELTA, 2008)

A Novel Genetic Algorithm with Cell Crossover for Circuit Design Optimization. - Zhiguo Bao; Takahiro Watanabe (ISCAS, 2009)

A novel genetic algorithm with different structure selection for circuit design optimization. - Zhiguo Bao; Takahiro Watanabe (Artif. Life Robotics, 2009)

A hybrid architecture for efficient FPGA-based implementation of multilayer neural network. - Zhen Lin; Yiping Dong; Yan Li; Takahiro Watanabe (APCCAS, 2010)

Othello Solver based on a soft-core MIMD processor array. - Takayuki Mabuchi; Takahiro Watanabe; Retsu Moriwaki; Yuji Aoyama; Amarjargal Gundjalam; Yuichiro Yamaji; Hironari Nakada; Minoru Watanabe (FPT, 2010)

High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels. - Yiping Dong; Zhen Lin; Yan Li; Takahiro Watanabe (ISCAS, 2010)

Mixed constrained image filter design using particle swarm optimization. - Zhiguo Bao; Takahiro Watanabe (Artif. Life Robotics, 2010)

Erratum to: Mixed constrained image filter design using particle swarm optimization. - Zhiguo Bao; Takahiro Watanabe (Artif. Life Robotics, 2010)

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover. - Zhiguo Bao; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power. - Xin Jiang 003; Ran Zhang 005; Takahiro Watanabe (ASICON, 2011)

A behavior-based reconfigurable cache for the low-power embedded processor. - Jiongyao Ye; Jiannan Jin; Takahiro Watanabe (ASICON, 2011)

Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. - Takahiro Watanabe; Minoru Watanabe (FPL, 2011)

An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

Efficient GA Approach Combined with Taguchi Method for Mixed Constrained Circuit Design. - Yiwen Su; Zhiguo Bao; Fangfang Wang; Takahiro Watanabe (ICCSA Workshops, 2011)

New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM. - Ce Li 006; Yiping Dong; Takahiro Watanabe (ISLPED, 2011)

Developing a Real-Time System for Measuring the Consumption of Seasoning. - Mayumi Ueda; Takuya Funatomi; Atsushi Hashimoto 001; Takahiro Watanabe; Michihiko Minoh (ISM, 2011)

Fault-tolerant image filter design using particle swarm optimization. - Zhiguo Bao; Fangfang Wang; Xiaoming Zhao; Takahiro Watanabe (Artif. Life Robotics, 2011)

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture. - Ce Li 006; Yiping Dong; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism. - Jiongyao Ye; Yingtao Hu; Hongfeng Ding; Takahiro Watanabe (IEICE Trans. Inf. Syst., 2011)

An Adaptive Various-Width Data Cache for Low Power Design. - Jiongyao Ye; Yu Wan 002; Takahiro Watanabe (IEICE Trans. Inf. Syst., 2011)

A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction. - Jiongyao Ye; Yu Wan 002; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. - Takahiro Watanabe; Minoru Watanabe (ARC, 2012)

High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. - Takahiro Watanabe; Minoru Watanabe (IPDPS Workshops, 2012)

0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. - Takahiro Watanabe; Minoru Watanabe (ISVLSI, 2012)

Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. - Takahiro Watanabe; Minoru Watanabe (MWSCAS, 2012)

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture. - Ce Li 006; Yiping Dong; Takahiro Watanabe (IEICE Trans. Inf. Syst., 2012)

Region Oriented Routing FPGA Architecture for Dynamic Power Gating. - Ce Li 006; Yiping Dong; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems. - Jiongyao Ye; Hongfeng Ding; Yingtao Hu; Takahiro Watanabe (J. Inf. Process., 2012)

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. - Takahiro Watanabe; Minoru Watanabe (SIGARCH Comput. Archit. News, 2012)

A sorting-based IO connection assignment for flip-chip designs. - Ran Zhang 005; Xue Wei; Takahiro Watanabe (ASICON, 2013)

Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors. - Huatao Zhao; Jiongyao Ye; Yuxin Sun; Takahiro Watanabe (ASICON, 2013)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)

An Efficient Algorithm for 3D NoC Architecture Optimization. - Xin Jiang 003; Ran Zhang 005; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A randomized algorithm for the fixed-length routing problem. - Tieyuan Pan; Ran Zhang 005; Yasuhiro Takashima; Takahiro Watanabe (APCCAS, 2014)

Existence of a pure strategy equilibrium in finite symmetric games where payoff functions are integrally concave. - Takuya Iimura; Takahiro Watanabe (Discret. Appl. Math., 2014)

A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency. - Xin Jiang 003; Lian Zeng; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2014)

A performance enhanced dual-switch Network-on-Chip architecture. - Lian Zeng; Takahiro Watanabe (ASP-DAC, 2015)

A length matching routing method for disordered pins in PCB design. - Ran Zhang 005; Tieyuan Pan; Li Zhu; Takahiro Watanabe (ASP-DAC, 2015)

Application-specific shared last-level cache optimization for low-power embedded systems. - Huatao Zhao; Jiongyao Ye; Xian Su; Takahiro Watanabe (NEWCAS, 2015)

A Performance Enhanced Dual-switch Network-on-chip Architecture. - Lian Zeng; Xin Jiang 003; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design. - Ran Zhang 005; Tieyuan Pan; Li Zhu; Takahiro Watanabe (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Coordinated movement algorithm for accompanying cane robot. - Shunki Itadera; Takahiro Watanabe; Yasuhisa Hasegawa; Toshio Fukiida; Masanori Tanimoto; Izumi Kondo (MHS, 2016)

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. - Tieyuan Pan; Lian Zeng; Yasuhiro Takashima; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. - Tieyuan Pan; Li Zhu; Lian Zeng; Takahiro Watanabe; Yasuhiro Takashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip. - Lian Zeng; Tieyuan Pan; Xin Jiang 003; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Pure strategy equilibrium in finite weakly unilaterally competitive games. - Takuya Iimura; Takahiro Watanabe (Int. J. Game Theory, 2016)

An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip. - Jindun Dai; Xin Jiang 003; Takahiro Watanabe (CITS, 2017)

Osaka urban phased array radar network experiment. - Tomoo Ushio; Shigeharu Shimamura; Hiroshi Kikuchi; Fumihiko Mizutani; Kenichi Naito; Takahiro Watanabe; Masakazu Wada; Nobuhiro Takahashi (IGARSS, 2017)

Hybrid path-diversity-dominant output selection method for Network-on-Chip systems. - Jindun Dai; Wenda Ma; Xin Jiang 003; Takahiro Watanabe (ISOCC, 2017)

High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC. - Xin Jiang 003; Xiangyang Lei; Lian Zeng; Takahiro Watanabe (ISQED, 2017)

An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips. - Jindun Dai; Xin Jiang 003; Renjie Li; Takahiro Watanabe (MCSoC, 2017)

High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem. - Xin Jiang 003; Xiangyang Lei; Lian Zeng; Takahiro Watanabe (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA. - Tingyu Zhou; Tieyuan Pan; Zhiguo Bao; Takahiro Watanabe (ICSAI, 2018)

PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs. - Jindun Dai; Renjie Li; Xin Jiang 003; Takahiro Watanabe (ISQED, 2018)

Nonlinear Optimization Method Based on Stochastic Gradient Descent for Fast Convergence. - Takahiro Watanabe; Hitoshi Iima (SMC, 2018)

Binary action games: Deviation properties, semi-strict equilibria and potentials. - Takuya Iimura; Pierre von Mouche; Takahiro Watanabe (Discret. Appl. Math., 2018)

Wavelength-Selective Fog-Computing Network for Big-Data Analytics of Wireless Data. - Michael Conrad Meyer; Yu Wang 064; Takahiro Watanabe (ICEIC, 2019)

Improvement of Agile Software Development Process Based on Automotive SPICE: A Case Study. - Toshihiro Komiyama; Shigeo Konno; Takahiro Watanabe; Shigenori Matsui; Masakazu Kase; Issei Igarashi (EuroSPI, 2019)

Low-Cost Congestion Detection Mechanism for Networks-on-Chip. - Zhengqian Han; Michael Conrad Meyer; Xin Jiang 003; Takahiro Watanabe (MCSoC, 2019)

A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip. - Yaoying Luo; Michael Conrad Meyer; Xin Jiang 003; Takahiro Watanabe (MCSoC, 2019)

Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip. - Michael Conrad Meyer; Yu Wang 064; Takahiro Watanabe (MCSoC, 2019)

A Traffic-Robust Routing Algorithm for Network-on-Chip Systems. - Siying Xu; Michael Conrad Meyer; Xin Jiang 003; Takahiro Watanabe (MCSoC, 2019)

Filter router: An enhanced router design for efficient stacked shared cache network. - Huatao Zhao; Xu Jia; Takahiro Watanabe (IEICE Electron. Express, 2019)

A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems. - Huatao Zhao; Jiongyao Ye; Takahiro Watanabe (J. Inf. Process., 2019)

An Interval-based Mapping Algorithm for Multi-shape Tasks on Dynamic Partial Reconfigurable FPGAs. - Tingyu Zhou; Tieyuan Pan; Michael Conrad Meyer; Yiping Dong; Takahiro Watanabe (IPDPS Workshops, 2020)

A Fast Online Task Placement Algorithm for Three-Dimensional Dynamic Partial Reconfigurable Devices. - Tingyu Zhou; Tieyuan Pan; Michael Conrad Meyer; Yiping Dong; Takahiro Watanabe (IEEE Access, 2020)

Multi-Shape Task Placement Algorithm Based on Low Fragmentation Resource Management on 2D Heterogeneous Dynamic Partial Reconfigurable Devices. - Tingyu Zhou; Tieyuan Pan; Michael Conrad Meyer; Yiping Dong; Takahiro Watanabe (IEEE Access, 2020)

Two-person pairwise solvable games. - Takuya Iimura; Toshimasa Maruta; Takahiro Watanabe (Int. J. Game Theory, 2020)

Selection System of Robot Type for Cell Assembly Production (Production Efficiency Comparison of Single and Double Arm Robot). - Hidehiko Yamamoto; Takahiro Watanabe; Takayoshi Yamada (J. Robotics Netw. Artif. Life, 2020)

Real-Time Cost Minimization of Fog Computing in Mobile-Base-Station Networked Disaster Areas. - Michael Conrad Meyer; Yu Wang 064; Takahiro Watanabe (IEEE Open J. Comput. Soc., 2021)

Self-restructuring of Mesh-Connected Processor Arrays with Spares Assigned on Rotated Orthogonal Side. - Itsuo Takanami; Masaru Fukushi; Takahiro Watanabe (Trans. Comput. Sci., 2021)