An experimental 256-Mb DRAM with boosted sense-ground scheme. - Mikio Asakura; Tsukasa Ooishi; Masaki Tsukude; Shigeki Tomishima; Takahisa Eimori; Hideto Hidaka; Yoshikazu Ohno; Kazutani Arimoto; Kazuyasu Fujishima; Tadashi Nishimura; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. - Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Fukashi Morishita; Kazutarni Arimoto; Kazuyasu Fujishima; Yasuo Inoue; et al. (IEEE J. Solid State Circuits, 1994)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)