Partitioning and Placement Technique for CMOS Gate Arrays. - Gotaro Odawara; Takahisa Hiraide; Osamu Nishina (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

BIST-Aided Scan Test - A New Method for Test Cost Reduction. - Takahisa Hiraide; Kwame Osei Boateng; Hideaki Konishi; Koichi Itaya; Michiaki Emori; Hitoshi Yamanaka; Takashi Mochiyama (VTS, 2003)

Delay defect screening for a 2.16GHz SPARC64 microprocessor. - Noriyuki Ito; Akira Kanuma; Daisuke Maruyama; Hitoshi Yamanaka; Tsuyoshi Mochizuki; Osamu Sugawara; Chihiro Endoh; Masahiro Yanagida; Takeshi Kono; Yutaka Isoda; Kazunobu Adachi; Takahisa Hiraide; et al. (ASP-DAC, 2006)

The Application of BIST-Aided Scan Test for Real Chips. - Hideaki Konishi; Michiaki Emori; Takahisa Hiraide (ATS, 2006)

Test Data Compression of 100x for Scan-Based BIST. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (ITC, 2006)

Test Data Compression for Scan-Based BIST Aiming at 100x Compression Rate. - Masayuki Arai; Satoshi Fukumoto; Kazuhiko Iwasaki; Tatsuru Matsuo; Takahisa Hiraide; Hideaki Konishi; Michiaki Emori; Takashi Aikyo (IEICE Trans. Inf. Syst., 2008)