Multicore Power Management Utilizing Error-Predicting Flip-flop. - Toshinori Sato; Takahito Yoshiki; Takanori Hayashida (CISIS, 2011)

Importance of Single-Core Performance in the Multicore Era. - Toshinori Sato; Hideki Mori; Rikiya Yano; Takanori Hayashida (ACSC, 2012)

Dynamically reducing overestimated design margin of MultiCores. - Toshinori Sato; Takanori Hayashida; Ken Yano (HPCS, 2012)

Guidelines for mitigating NBTI degradation in on-chip memories. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (ISCIT, 2012)

Analysis of SER Improvement by Radiation Hardened Latches. - Ken Yano; Takanori Hayashida; Toshinori Sato (PRDC, 2012)

A Selective Replacement Method for Timing-Error-Predicting flip-Flops. - Yuji Kunitake; Toshinori Sato; Hiroto Yasuura; Takanori Hayashida (J. Circuits Syst. Comput., 2012)

Improving timing error tolerance without impact on chip area and power consumption. - Ken Yano; Takanori Hayashida; Toshinori Sato (ISQED, 2013)