Evaluation of on-chip transmission line interconnect using wire length distribution. - Junpei Inoue; Hiroyuki Ito; Shinichiro Gomi; Takanori Kyogoku; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2005)

Wire Length Distribution Model Considering Core Utilization for System on Chip. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISVLSI, 2005)

Prediction of delay time for future LSI using on-chip transmission line interconnects. - Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada 001; Kazuya Masu (SLIP, 2005)

Wire Length Distribution Model for System LSI. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)