A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

A 30-ns 256-Mb DRAM with a multidivided array structure. - Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; Tatsuya Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; et al. (IEEE J. Solid State Circuits, 1993)

A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. - Takanori Saeki; Yuji Nakaoka; Mamoru Fujita; Akihito Tanaka; Kyoichi Nagata; Kenichi Sakakibara; Tatsuya Matano; Yukio Hoshino; Kazutaka Miyano; Satoshi Isa; Shigeyuki Nakazawa; Eiichiro Kakehashi; et al. (IEEE J. Solid State Circuits, 1996)

The direct skew detect synchronous mirror delay (Direct SMD) for ASICs. - Takanori Saeki; Koichiro Minami; Hiroshi Yoshida; Hisamitsu Suzuki (CICC, 1998)

A direct-skew-detect synchronous mirror delay for application-specific integrated circuits. - Takanori Saeki; Koichiro Minami; Hiroshi Yoshida; Hisamitsu Suzuki (IEEE J. Solid State Circuits, 1999)

A 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for "clock on demand". - Takanori Saeki; Masafumi Mitsuishi; Hiroaki Iwaki; Mitsuaki Tagishi (IEEE J. Solid State Circuits, 2000)