A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture. - Toshihiko Hirose; Hirotada Kuriyama; Shuji Murakami; Kojiro Yuzuriha; Takao Mukai; Kazuhito Tsutsumi; Yasumasa Nishimura; Yoshio Kohno; Kenji Anami (IEEE J. Solid State Circuits, 1990)