Design and verification of large-scale computers by using DDL. - Nobuaki Kawato; Takao Saito; Fumihiro Maruyama; Takao Uehara (DAC, 1979)

A CAD system for logic design based on frames and demons. - Takao Saito; Takao Uehara; Nobuaki Kawato (DAC, 1981)

An interactive logic synthesis system based upon AI techniques. - Nobuaki Kawato; Takao Uehara; Sadaki Hirose; Takao Saito (DAC, 1982)

A verification technique for hardware designs. - Fumihiro Maruyama; Takao Uehara; Nobuaki Kawato; Takao Saito (DAC, 1982)

A rule-based logic circuit synthesis system for CMOS gate arrays. - Takao Saito; Hiroyuki Sugimoto; Masami Yamazaki; Nobuaki Kawato (DAC, 1986)