A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. - Takao Sato; Masao Nakajima; Takao Sukemura; Gensuke Goto (VLSI, 1991)

A 54*54-b regularly structured tree multiplier. - Gensuke Goto; Tomio Sato; Masao Nakajima; Takao Sukemura (IEEE J. Solid State Circuits, 1992)