2.8-Gb/s 176-mW byte-interleaved and 3.0-Gb/s 118-mW bit-interleaved 8: 1 multiplexers with a 0.15-μm CMOS technology. - Masakazu Kurisu; Makoto Kaneko; Tetsuyuki Suzaki; Akira Tanabe; Mitsuhiro Togo; Akio Furukawa; Takao Tamura; Ken Nakajima; Kazuyoshi Yoshida (IEEE J. Solid State Circuits, 1996)

A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-talk preamplifier. - Akira Tanabe; Masaaki Soda; Yasushi Nakahara; Takao Tamura; Kazuyoshi Yoshida; Akio Furukawa (IEEE J. Solid State Circuits, 1998)