Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. - Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato 001; Takao Onoye (CICC, 2006)

Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. - Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato 001; Takao Onoye (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Decoupling capacitance allocation for timing with statistical noise model and timing analysis. - Takashi Enami; Masanori Hashimoto; Takashi Sato 001 (ICCAD, 2008)

Statistical Timing Analysis Considering Spatially and Temporally Correlated Dynamic Power Supply Noise. - Takashi Enami; Shinyu Ninomiya; Masanori Hashimoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation. - Takashi Enami; Shinyu Ninomiya; Kenichi Shinkai; Shinya Abe; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. - Takashi Enami; Takashi Sato 001; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

DMA-driven control method for low power sensor node. - Takashi Enami; Kentaro Kawakami; Hiroshi Yamazaki (WiSNet, 2015)