A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory. - Satoshi Kaneko; Hiroyuki Kondo; Norio Masui; Koichi Ishimi; Teruyuki Itou; Masayuki Satou; Naoto Okumura; Yukari Takata; Hirokazu Takata; Mamoru Sakugawa; Takashi Higuchi; Sugako Ohtani; et al. (IEEE J. Solid State Circuits, 2004)

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. - Hiroyuki Kondo; Masami Nakajima; Norio Masui; Sugako Otani; Naoto Okumura; Yukari Takata; Takashi Nasu; Hirokazu Takata; Takashi Higuchi; Mamoru Sakugawa; Hayato Fujiwara; Kazuya Ishida; et al. (IEEE J. Solid State Circuits, 2008)

3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. - Hayato Kimura 003; Hideyuki Noda; Hisaaki Watanabe; Takashi Higuchi; Ryosaku Kobayashi; Masayuki Utsuno; Fumitake Takami; Sugako Otani; Masayuki Ito; Yasuhisa Shimazaki; Naoki Yada; Hiroyuki Kondo (ISSCC, 2017)