1.3- mu m CMOS/bipolar standard cell library for VLSI computers. - Takashi Hotta; Kouzaburou Kurita; Hideo Maejima; Masahiro Iwamura; Shigeya Tanaka; Tadaaki Bandoh; Tatsumi Yamauchi; Atsuo Hotta (IEEE J. Solid State Circuits, 1988)

A high performance BiCMOS 32-bit microprocessor. - Yasuhiro Nakatsuka; Takashi Hotta; Shigeya Tanaka; Tadaaki Bandoh; Ryuichi Satomura; Syuichi Nakagami; Tetsuo Nakano; Atsuo Hotta; Takashi Moriyama; Shigemi Adachi; Shoji Iwamoto (ICCD, 1989)

A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library. - Takashi Hotta; Tadaaki Bandoh; Atsuo Hotta; Tetsuo Nakano; Shoji Iwamoto; Shigemi Adachi (IEEE J. Solid State Circuits, 1990)

PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor. - Kozaburo Kurita; Takashi Hotta; Tetsuo Nakano; Nobuaki Kitamura (IEEE J. Solid State Circuits, 1991)

3.3-V BiCMOS circuit techniques for a 120-MHz RISC microprocessor. - Fumio Murabayashi; Takashi Hotta; Shigeya Tanaka; Tatsumi Yamauchi; Hiromichi Yamada; Tetsuo Nakano; Yutaka Kobayashi; Tadaaki Bandoh (IEEE J. Solid State Circuits, 1994)

A 120-MHz BiCMOS superscalar RISC processor. - Shigeya Tanaka; Takashi Hotta; Fumio Murabayashi; Hiromichi Yamada; Shoji Yoshida; Kotaro Shimamura; Koyo Katsura; Tadaaki Bandoh; Koichi Ikeda; Kenji Matsubara; Kouji Saitou; Tetsuo Nakano; et al. (IEEE J. Solid State Circuits, 1994)

A superscalar RISC processor with pseudo vector processing feature. - Kotaro Shimamura; Shigeya Tanaka; Tetsuya Shimomura; Takashi Hotta; Eiki Kamada; Hideo Sawamoto; Teruhisa Shimizu; Kisaburo Nakazawa (ICCD, 1995)

A 13.3ns double-precision floating-point ALU and multiplier. - Hiromichi Yamada; Takashi Hotta; Takahiro Nishiyama; Fumio Murabayashi; Tatsumi Yamauchi; Hideo Sawamoto (ICCD, 1995)

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor. - Fumio Murabayashi; Tatsumi Yamauchi; Hiromichi Yamada; Takahiro Nishiyama; Kotaro Shimamura; Shigeya Tanaka; Takashi Hotta; Teruhisa Shimizu; Hideo Sawamoto (IEEE J. Solid State Circuits, 1996)

A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller. - Kotaro Shimamura; Yuichiro Morita; Yoshitaka Takahashi; Takashi Hotta; Shigeta Ueda; Mikiya Nohara; Mitsuyasu Kido; Seji Tanaka; Kazuhiro Imaie; Koji Sakamoto; Tatsuhito Nakajima (IEEE Real Time Technology and Applications Symposium, 1998)

Instruction fetch and dispatch scheme with flag-in-cache/in-IBR. - Shoji Yoshida; Shigeya Tanaka; Kotaro Matsuo; Takashi Hotta; Hideo Sawamoto; Teruhisa Shimizu (Syst. Comput. Jpn., 1998)