Coarse-grained dynamically reconfigurable architecture with flexible reliability. - Dawood Alnajiar; Younghun Ko; Takashi Imagawa; Hiroaki Konoura; Masayuki Hiromoto; Yukio Mitsuyama; Masanori Hashimoto; Hiroyuki Ochi; Takao Onoye (FPL, 2009)

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (SoCC, 2010)

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (DATE, 2013)

High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hiroyuki Ochi; Takashi Imagawa; Shinichi Noda; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye (ReConFig, 2013)

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2013)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices. - Hiroaki Konoura; Takashi Imagawa; Yukio Mitsuyama; Masanori Hashimoto; Takao Onoye (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Image smoothing using spatial iterative methods based on accelerated iterative shrinkage. - Dabwitso Kasauka; Hiroshi Tsutsui; Hiroyuki Okuhata; Takashi Imagawa; Yoshikazu Miyanaga (APSIPA, 2015)

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. - Masanori Hashimoto; Dawood Alnajiar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera (ASP-DAC, 2015)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2015)

Image smoothing in the spatial domain using multigrid conjugate gradient methods based on accelerated iterative shrinkage. - Dabwitso Kasauka; Hiroshi Tsutsui; Seijiro Imai; Takashi Imagawa; Hiroyuki Okuhata; Yoshikazu Miyanaga (APSIPA, 2016)

Processing time reduction of tone mapping based on iterative shrinkage smoothing using parallel processing. - Seijiro Imai; Dabwitso Kasauka; Hiroshi Tsutsui; Takashi Imagawa; Hiroyuki Okuhata; Yoshikazu Miyanaga (ISPACS, 2016)

FHD loss-less video communication over 8 × 8 MIMO-OFDM. - Yoshikazu Miyanaga; Hiroshi Tsutsui; Takashi Imagawa (ISCIT, 2017)

Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain. - Takashi Imagawa; Koki Honda; Hiroyuki Ochi (SoCC, 2017)

Selectable grained reconfigurable architecture (SGRA) and its design automation. - Ryosuke Koike; Takashi Imagawa; Roberto Yusi Omaki; Hiroyuki Ochi (SoCC, 2017)

Development of Real-time FHD Loss-Less Video Communication over an $8 times 8$ MIMO-OFDM System. - Yoshikazu Miyanaga; Junji Yamano; Masaki Miura; Tohru Gotoh; Takashi Imagawa; Hiroshi Tsutsui (APSIPA, 2018)

Development of High Performance RF Modules Used in Real-time FHD Video Communication over 8x8 MIMO-OFDM System. - Yoshikazu Miyanaga; Masaki Miura; Tohru Gotoh; Junji Yamano; Takashi Imagawa; Hiroshi Tsutsui (ISPACS, 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

MUX Granularity Oriented Iterative Technology Mapping for Implementing Compute-Intensive Applications on Via-Switch FPGA. - Takashi Imagawa; Jaehoon Yu; Masanori Hashimoto; Hiroyuki Ochi (DATE, 2021)

Finding All Solutions of Multi-terminal Numberlink Problem Utilizing Top-down ZDD Construction. - Xuanqi Li; Takashi Imagawa; Hiroyuki Ochi (ASICON, 2023)

Approximate Logarithmic Multipliers Using Half Compensation with Two Line Segments. - Renya Makimoto; Takashi Imagawa; Hiroyuki Ochi (SOCC, 2023)

A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. - Ippei Tanaka; Naoyuki Miyagawa; Tomoya Kimura; Takashi Imagawa; Hiroyuki Ochi (IPSJ Trans. Syst. LSI Des. Methodol., 2023)

A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. - Takashi Imagawa; Ryo Kishida; Yuki Koyama 005; Kazutoshi Kobayashi; Takefumi Miyoshi (QCE, 2024)