An 80-ns 1-Mb flash memory with on-chip erase/erase-verify controller. - Koichi Seki; Hitoshi Kume; Yuzuru Ohji; Takashi Kobayashi 002; Atushi Hiraiwa; Takeshi Nishida; Takeshi Wada; Kazuhiro Komori; Kazuto Izawa; Toshiaki Nishimoto; Yasuroh Kubota; Kazuyoshi Shoji (IEEE J. Solid State Circuits, 1990)

Performance Model of Interference Avoidance Policy Using Stochastic Petri Nets. - Takashi Kobayashi 002; Kenzo Kurihara (PNPM, 1991)

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. - Takayuki Kawahara; Takashi Kobayashi 002; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; T. Adachi; Masataka Kato; Akihiko Sato; J. Yugami; Hitoshi Kume; Katsutaka Kimura (IEEE J. Solid State Circuits, 1996)

Internal voltage generator for low voltage, quarter-micrometer flash memories. - Takayuki Kawahara; Syun-ichi Saeki; Yusuke Jyouno; Naoki Miyamoto; Takashi Kobayashi 002; Katsutaka Kimura (IEEE J. Solid State Circuits, 1998)

Single-electron memory for giga-to-tera bit storage. - Kazuo Yano; Tomoyuki Ishii; Toshiaki Sano; Toshiyuki Mine; Fumio Murai; Takashi Hashimoto; Takashi Kobayashi 002; Tokuo Kure; Koichi Seki (Proc. IEEE, 1999)

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. - Hideaki Kurata; Shunichi Saeki; Takashi Kobayashi 002; Yoshitaka Sasago; Tsuyoshi Arigane; Kazuo Otsuga; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

A 130-nm CMOS 95-mm2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput. - Hideaki Kurata; Shunichi Saeki; Takashi Kobayashi 002; Yoshitaka Sasago; Tsuyoshi Arigane; Keiichi Yoshida; Yoshinori Takase; Takayuki Yoshitake; Osamu Tsuchiya; Yoshinori Ikeda; Shunichi Narumi; Michitaro Kanamitsu; et al. (IEICE Trans. Electron., 2006)

A 126 mm2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology. - Hideaki Kurata; Satoshi Noda; Yoshitaka Sasago; Kazuo Otsuga; Tsuyoshi Arigane; Tetsufumi Kawamura; Takashi Kobayashi 002; Hitoshi Kume; Kazuki Homma; Teruhiko Ito; Yoshinori Sakamoto; Masahiro Shimizu; et al. (IEICE Trans. Electron., 2007)

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories. - Kazuo Otsuga; Hideaki Kurata; Satoshi Noda; Yoshitaka Sasago; Tsuyoshi Arigane; Tetsufumi Kawamura; Takashi Kobayashi 002 (IEICE Trans. Electron., 2007)