Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond. - Noriaki Oda; Hiroyuki Kunishima; Takashi Kyouno; Kazuhiro Takeda; Tomoaki Tanaka; Toshiyuki Takewaki; Masahiro Ikeda (IEICE Trans. Electron., 2006)