A 3.84 GIPS integrated memory array processor with 64 processing elements and a 2-Mb SRAM. - Nobuyuki Yamashita; Tohru Kimura; Yoshihiro Fujita; Yoshiharu Aimoto; Takashi Manabe; Shin'ichiro Okazaki; Kazuyuki Nakamura; Masakazu Yamashina (IEEE J. Solid State Circuits, 1994)

Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. - Tohru Kimura; Kazuyuki Nakamura; Yoshiharu Aimoto; Takashi Manabe; Nobuyuki Yamashita; Yoshihiro Fujita; Shin'ichiro Okazaki; Masakazu Yamashina (IEEE J. Solid State Circuits, 1995)

Dynamic Stability Analysis of Flow-Conveying Pipe with Two Lumped Masses by Domain Decomposition BEM. - Takashi Manabe; Nobuyoshi Tosaka; Toshio Honma (PDPTA, 2000)