The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. - Takashi Midorikawa; Takayuki Kamei; Toshihiro Hanawa; Hideharu Amano (ASP-DAC, 1998)

Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. - Yasuki Tanabe; Takashi Midorikawa; Daisuke Shiraishi; Masayoshi Shigeno; Toshihiro Hanawa; Hideharu Amano (PDPTA, 2003)

Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. - Masato Sumiyoshi; Takashi Midorikawa; Yasuki Tanabe; Hideharu Amano (PDCS, 2004)

The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). - Takashi Midorikawa; Daisuke Shiraishi; Masayoshi Shigeno; Yasuki Tanabe; Toshihiro Hanawa; Hideharu Amano (Parallel Comput., 2005)