Design Considerations for 32-bit Microprocessor TX3. - Kosei Okamoto; Misao Miyata; Hidechika Kishigami; Takashi Miyamori; Tai Sato (COMPCON, 1988)

The effectiveness of TRONCHIP instructions in the TX1 system. - Hidechika Kishigami; Takashi Miyamori; Misao Miyata (COMPCON, 1989)

A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications. - Takashi Miyamori; Kunle Olukotun (FCCM, 1998)

REMARC: Reconfigurable Multimedia Array Coprocessor (Abstract). - Takashi Miyamori; Kunle Olukotun (FPGA, 1998)

A single-chip MPEG-2 codec based on customizable media microprocessor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (CICC, 2002)

Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. - Atsushi Mizuno; Kazuyoshi Kohno; Ryuichiro Ohyama; Takahiro Tokuyoshi; Hironori Uetani; Hans Eichel; Takashi Miyamori; Nobu Matsumoto; Masataka Matsui (ICCD, 2002)

Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. - Jun Tanahe; Yasuhiro Taniguchi; Takashi Miyamori; Yukimasa Miyamoto; Hideki Takeda; Masaya Tarui; Hiromitsu Nakayama; Nohuyulu Takeda; Kenichi Maeda; Masataka Matsui (CICC, 2003)

A single-chip MPEG-2 codec based on customizable media embedded processor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (IEEE J. Solid State Circuits, 2003)

Development of Image Recognition Processor Based on Configurable Processor. - Takashi Miyamori; Jun Tanabe; Yasuhiro Taniguchi; Kenji Furukawa; Tatsuo Kozakaya; Hiroaki Nakai; Yukimasa Miyamoto; Ken-ichi Maeda; Masataka Matsui (J. Robotics Mechatronics, 2005)

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology. - Shuou Nomura; Fumihiko Tachibana; Tetsuya Fujita; Chen Kong Teh; Hiroyuki Usui; Fumiyuki Yamane; Yukimasa Miyamoto; Chaiyasit Kumtornkittikul; Hiroyuki Hara; Takahiro Yamashita; Jun Tanabe; Masaru Uchiyama; et al. (ISSCC, 2008)

A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. - Takahisa Wada; Shunichi Ishiwata; Katsuyuki Kimura; Keiri Nakanishi; Masato Sumiyoshi; Takashi Miyamori; Masaki Nakagawa (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Signal and power integrity for SoCs. - Don Draper; Fabio Campi; Ram Krishnamurthy 001; Takashi Miyamori; Shannon Morton; Willy Sansen; Vladimir Stojanovic; John T. Stonick (ISSCC, 2010)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)

A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications. - Yasuki Tanabe; Masato Sumiyoshi; Manabu Nishiyama; Itaru Yamazaki; Shinsuke Fujii; Katsuyuki Kimura; Takuma Aoyama; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2012)

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. - Hui Xu; Jun Tanabe; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Takashi Miyamori (VLSIC, 2012)

A near-future prediction method for low power consumption on a many-core processor. - Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto (DATE, 2013)

Development of low power many-core SoC for multimedia applications. - Takashi Miyamori; Hui Xu; Takeshi Kodaka; Hiroyuki Usui; Toru Sano; Jun Tanabe (DATE, 2013)

An evaluation of an energy efficient many-core SoC with parallelized face detection. - Hiroyuki Usui; Jun Tanabe; Toru Sano; Hui Xu; Takashi Miyamori (ASP-DAC, 2014)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. - Takashi Miyamori; Hui Xu; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Jun Tanabe (IEICE Trans. Electron., 2014)

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications. - Jun Tanabe; Toru Sano; Yutaka Yamada; Tomoki Watanabe; Mayu Okumura; Manabu Nishiyama; Tadakazu Nomura; Kazushige Oma; Nobuhiro Sato; Moriyasu Banno; Hiroo Hayashi; Takashi Miyamori (ISSCC, 2015)