110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock. - Toshiro Takahashi; Takashi Muto; Yuji Shirai; Fumihiko Shirotori; Yoshifumi Takada; Akira Yamagiwa; Akira Nishida; Atsuo Hotta; Tadashi Kiyuna (IEEE J. Solid State Circuits, 1999)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. - Takashi Kawamoto; Takayasu Norimatsu; Kenji Kogo; Fumio Yuki; Norio Nakajima; Masatoshi Tsuge; Tatsunori Usugi; Tomofumi Hokari; Hideki Koba; Takemasa Komori; Junya Nasu; Tsuneo Kawamata; et al. (ISSCC, 2015)

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. - Takayasu Norimatsu; Takashi Kawamoto; Kenji Kogo; Naohiro Kohmu; Fumio Yuki; Norio Nakajima; Takashi Muto; Junya Nasu; Takemasa Komori; Hideki Koba; Tatsunori Usugi; Tomofumi Hokari; et al. (ISSCC, 2016)

6.4 An APS-H-Size 250Mpixel CMOS image sensor using column single-slope ADCs with dual-gain amplifiers. - Hirofumi Totsuka; Toshiki Tsuboi; Takashi Muto; Daisuke Yoshida; Yasushi Matsuno; Masanobu Ohmura; Hidekazu Takahashi; Katsuhito Sakurai; Takeshi Ichikawa; Hiroshi Yuzurihara; Shunsuke Inoue (ISSCC, 2016)

A 1.8e-rms Temporal Noise Over 110-dB-Dynamic Range 3.4µm Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter. - Masahiro Kobayashi; Yusuke Onuki; Kazunari Kawabata; Hiroshi Sekine; Toshiki Tsuboi; Takashi Muto; Takeshi Akiyama; Yasushi Matsuno; Hidekazu Takahashi; Toru Koizumi 002; Katsuhito Sakurai; Hiroshi Yuzurihara; et al. (IEEE J. Solid State Circuits, 2018)