Design and Implementation of a High Speed Microprocessor Simulator BurstScalar. - Takashi Nakada; Hiroshi Nakashima (MASCOTS, 2004)

Design and Implementation of aWorkload Specific Simulator. - Takashi Nakada; Tomoaki Tsumura; Hiroshi Nakashima (Annual Simulation Symposium, 2006)

An accurate and efficient simulation-based analysis for worst case interruption delay. - Hiroshi Nakashima; Masahiro Konishi; Takashi Nakada (CASES, 2006)

An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators. - Masahiro Yano; Toru Takasaki; Takashi Nakada; Hiroshi Nakashima (Annual Simulation Symposium, 2007)

An Efficient Analysis of Worst Case Flush Timings for Branch Predictors. - Masahiro Konishi; Takashi Nakada; Tomoaki Tsumura; Hiroshi Nakashima; Hiroaki Takada (Inf. Media Technol., 2007)

A Functional Unit with Small Variety of Highly Reliable Cells. - Kouki Suzuki; Takashi Nakada; Masaki Nakanishi; Shigeru Yamashita; Yasuhiko Nakashima (PRDC, 2008)

A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions. - Hiroshi Nakashima; Masahiro Konishi; Takashi Nakada (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

An Instruction Decomposition Method for Reconfigurable Decoders. - Kazuhiro Yoshimura; Takashi Nakada; Yasuhiko Nakashima (IWIA, 2010)

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. - Jun Yao 001; Ryoji Watanabe; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima; Kazutoshi Kobayashi (PRDC, 2010)

An efficient and reliable 1.5-way processor by fusion of space and time redundancies. - Jun Yao 001; Ryoji Watanabe; Kazuhiro Yoshimura; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima (DSN Workshops, 2011)

LAPP: A Low Power Array Accelerator with Binary Compatibility. - Naveen Devisetti; Takuya Iwakami; Kazuhiro Yoshimura; Takashi Nakada; Jun Yao 001; Yasuhiko Nakashima (IPDPS Workshops, 2011)

An Instruction Mapping Scheme for FU Array Accelerator. - Kazuhiro Yoshimura; Takuya Iwakami; Takashi Nakada; Jun Yao 001; Hajime Shimada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2011)

RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path. - Yukihiro Sasagawa; Jun Yao 001; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. - Hiroki Noguchi; Kumiko Nomura; Keiko Abe; Shinobu Fujita; Eishi Arima; Kyundong Kim; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (DATE, 2013)

Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mapping. - Toshiya Komoda; Shingo Hayashi; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (ICCD, 2013)

Performance modeling for designing NoC-based multiprocessors. - Takashi Nakada; Shinobu Miwa; Keisuke Y. Yano; Hiroshi Nakamura (RSP, 2013)

Normally-off computing project: Challenges and opportunities. - Hiroshi Nakamura; Takashi Nakada; Shinobu Miwa (ASP-DAC, 2014)

Data-aware power management for periodic real-time systems with non-volatile memory. - Takashi Nakada; Takuya Shigematsu; Toshiya Komoda; Shinobu Miwa; Hiroshi Nakamura; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (NVMSA, 2014)

A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction. - Jun Yao 001; Yasuhiko Nakashima; Naveen Devisetti; Kazuhiro Yoshimura; Takashi Nakada (IEICE Trans. Inf. Syst., 2014)

Design Aid of Multi-core Embedded Systems with Energy Model. - Takashi Nakada; Kazuya Okamoto; Toshiya Komoda; Shinobu Miwa; Yohei Sato; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (Inf. Media Technol., 2014)

Energy-Efficient Continuous Task Scheduling for Near Real-Time Periodic Tasks. - Takashi Nakada; Hiroyuki Yanagihashi; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi; Hiroshi Nakamura (DSDIS, 2015)

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches. - Eishi Arima; Hiroki Noguchi; Takashi Nakada; Shinobu Miwa; Susumu Takeda; Shinobu Fujita; Hiroshi Nakamura (ICCD, 2015)

Runtime multi-optimizations for energy efficient on-chip interconnections1. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (ICCD, 2015)

Normally-off power management for sensor nodes of global navigation satellite system. - Takashi Nakada; Hiroshi Nakamura; Toshifumi Nakamoto; Toru Shimizu (ISOCC, 2016)

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. - Hiroki Noguchi; Kazutaka Ikegami; Satoshi Takaya; Eishi Arima; Keiichi Kushida; Atsushi Kawasumi; Hiroyuki Hara; Keiko Abe; Naoharu Shimomura; Junichi Ito; Shinobu Fujita; Takashi Nakada; et al. (ISSCC, 2016)

An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Nakamura; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu (VLSI-SoC, 2016)

A Runtime Optimization Selection Framework to Realize Energy Efficient Networks-on-Chip. - Yuan He 002; Masaaki Kondo; Takashi Nakada; Hiroshi Sasaki 001; Shinobu Miwa; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2016)

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. - Hoang Gia Vu; Shinya Takamaeda-Yamazaki; Takashi Nakada; Yasuhiko Nakashima (FCCM, 2017)

Compression and Aggregation for Optimizing Information Transmission in Distributed CNN. - Takamasa Mitani; Hisakazu Fukuoka; Yuria Hiraga; Takashi Nakada; Yasuhiko Nakashima (CANDAR, 2017)

A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing. - Renyuan Zhang; Takashi Nakada; Yasuhiko Nakashima (CANDAR, 2017)

Energy-aware task scheduling for near real-time periodic tasks on heterogeneous multicore processors. - Takashi Nakada; Hiroyuki Yanagihashi; Hiroshi Nakamura; Kunimaro Imai; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi (VLSI-SoC, 2017)

An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation. - Takashi Nakada; Tomoki Hatanaka; Hiroshi Ueki; Masanori Hayashikoshi; Toru Shimizu; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2017)

Efficient Multitasking on FPGA Using HDL-Based Checkpointing. - Hoang Gia Vu; Takashi Nakada; Yasuhiko Nakashima (ARC, 2018)

A programmable analog calculation unit for vector computations. - Noriyuki Uetake; Renyuan Zhang; Takashi Nakada; Yasuhiko Nakashima (COOL CHIPS, 2018)

A Tree-Based Checkpointing Architecture for the Dependability of FPGA Computing. - Hoang Gia Vu; Shinya Takamaeda-Yamazaki; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2018)

Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing. - Renyuan Zhang; Noriyuki Uetake; Takashi Nakada; Yasuhiko Nakashima (IEEE Micro, 2018)

GPGPU Implementation of Variational Bayesian Gaussian Mixture Models. - Hiroki Nishimoto; Takashi Nakada; Yasuhiko Nakashima (CANDAR, 2019)

DiaNet: An Efficient Multi-Grained Re-configurable Neural Network in Silicon. - Renyuan Zhang; Yan Chen; Takashi Nakada; Yasuhiko Nakashima (SoCC, 2019)

Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation. - Renyuan Zhang; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Bayes without Bayesian Learning for Resisting Adversarial Attacks. - Thi Thu Thao Khong; Takashi Nakada; Yasuhiko Nakashima (CANDAR, 2020)

An Energy-Efficient Task Scheduling for Near Real-Time Systems on Heterogeneous Multicore Processors. - Takashi Nakada; Hiroyuki Yanagihashi; Kunimaro Imai; Hiroshi Ueki; Takashi Tsuchiya; Masanori Hayashikoshi; Hiroshi Nakamura (IEICE Trans. Inf. Syst., 2020)

Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing. - Ryuta Shingai; Yuria Hiraga; Hisakazu Fukuoka; Takamasa Mitani; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2020)

Flexible Bayesian Inference by Weight Transfer for Robust Deep Neural Networks. - Thi Thu Thao Khong; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2021)

Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing. - Hoang Gia Vu; Takashi Nakada; Yasuhiko Nakashima (Integr., 2021)

A Hybrid Bayesian-Convolutional Neural Network for Adversarial Robustness. - Thi Thu Thao Khong; Takashi Nakada; Yasuhiko Nakashima (IEICE Trans. Inf. Syst., 2022)