On Universal Single Transition Time Asynchronous State Assignments. - Takashi Nanya; Yoshihiro Tohma (IEEE Trans. Computers, 1978)

Universal Multicode STT State Assignments for Asynchronous Sequential Machines. - Takashi Nanya; Yoshihiro Tohma (IEEE Trans. Computers, 1979)

Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". - Teruhiko Yamada; Takashi Nanya (IEEE Trans. Computers, 1983)

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults. - Teruhiko Yamada; Takashi Nanya (IEEE Trans. Computers, 1984)

A design approach to self-checking processors. - Takashi Nanya; Toshiaki Kawamura (Syst. Comput. Jpn., 1986)

Error-secure and error-propagating concepts for strongly fault-secure systems. - Takashi Nanya; Toshiaki Kawamura (Syst. Comput. Jpn., 1987)

On Error Indication for Totally Self-Checking Systems. - Takashi Nanya; Toshiaki Kawamura (IEEE Trans. Computers, 1987)

A Note on Strongly Fault-Secure Sequential Circuits. - Takashi Nanya; Toshiaki Kawamura (IEEE Trans. Computers, 1987)

Multiple stuck-at fault testability of self-testing checkers. - Takashi Nanya; Samiha Mourad; Edward J. McCluskey (FTCS, 1988)

A higher level hardware design verification. - Atsushi Takahara; Takashi Nanya (ICCD, 1988)

Test research in Japan. - Hideo Fujiwara; Yuzo Takamatsu; Takashi Nanya; Teruhiko Yamada; Hideo Tamamoto; Kiyoshi Furuya (IEEE Des. Test, 1988)

Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors. - Takashi Nanya; Toshiaki Kawamura (IEEE Trans. Computers, 1988)

A strongly fault-secure and strongly code-disjoint realization of combinational circuits. - Takashi Nanya; Masatoshi Uchida (FTCS, 1989)

The Byzantine hardware fault model. - Takashi Nanya; Hendrik A. Goosen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Design of Fully Exercised SFS/SCD Logic Networks. - Takashi Nanya; Shin'ichi Hatakenaka; Ryuichi Onoo (FTCS, 1992)

Timing-reliability evaluation of asynchronous circuits based on different delay models. - Masashi Kuwako; Takashi Nanya (ASYNC, 1994)

TITAC: Design of A Quasi-Delay-Insensitive Microprocessor. - Takashi Nanya; Yoichiro Ueno; Hiroto Kagotani; Masashi Kuwako; Akihiro Takamura (IEEE Des. Test Comput., 1994)

A fault-tolerant multilayer neural network model and its properties. - Yasuo Tan; Takashi Nanya (Syst. Comput. Jpn., 1994)

Towards Totally Self-Checking Delay-Insensitive Systems. - Stanislaw J. Piestrak; Takashi Nanya (FTCS, 1995)

Gracefully Degrading Systems Using the Bulk-Synchronous Parallel Model with Randomised Shared Memory. - Andreas Savva; Takashi Nanya (FTCS, 1995)

Synthesis of two-phase quasi-delay-insensitive circuits from dependency graphs. - Hiroto Kagotani; Takashi Nanya (Syst. Comput. Jpn., 1995)

Logic circuit design for testability using orthonormal expansions. - Ryuichi Takahashi; Takashi Nanya (Syst. Comput. Jpn., 1995)

Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits. - Masaaki Maezawa; Itaru Kurosawa; Yoshio Kameda; Takashi Nanya (ASYNC, 1996)

An SNMP-based implementation of the adaptive distributed system-level diagnosis algorithm for LAN fault management. - Elias Procópio Duarte Jr.; Takashi Nanya (NOMS, 1996)

Hierarchical Adaptive Distributed System-Level Diagnosis Applied for SNMP-based Network Fault Management. - Elias Procópio Duarte Jr.; Takashi Nanya (SRDS, 1996)

Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications. - Sung-Bum Park; Takashi Nanya (VLSI Design, 1996)

Performance enhancement of two-phase quasi-delay-insensitive circuits. - Hiroto Kagotani; Takashi Nanya (Syst. Comput. Jpn., 1996)

TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. - Akihiro Takamura; Masashi Kuwako; Masashi Imai; Taro Fujii; Motokazu Ozawa; Izumi Fukasaku; Yoichiro Ueno; Takashi Nanya (ICCD, 1997)

Non-Broadcast Network Fault-Monitoring Based on System-Level Diagnosis. - Elias Procópio Duarte Jr.; Glenn Mansfield; Takashi Nanya; Shoichi Noguchi (Integrated Network Management, 1997)

Verification of asynchronous logic circuit design using process algebra. - Tomohiro Yoneda; Atsufumi Shibayama; Takashi Nanya (Syst. Comput. Jpn., 1997)

On the CSC Property of Signal Transition Graph Specifications for Asynchronous Circuit Design. - Mohit Sahni; Takashi Nanya (ASP-DAC, 1998)

TITAC-2: An Asynchronous 32-bit Microprocessor. - Akihiro Takamura; Motokazu Ozawa; Izumi Fukasaku; Taro Fujii; Yoichiro Ueno; Masashi Imai; Masashi Kuwako; Takashi Nanya (ASP-DAC, 1998)

Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. - Yoshio Kameda; Stanislav Polonsky; Masaaki Maezawa; Takashi Nanya (ASYNC, 1998)

Improving the dependability of network management systems. - Elias Procópio Duarte Jr.; Glenn Mansfield; Takashi Nanya; Shoichi Noguchi (Int. J. Netw. Manag., 1998)

Stuck-at-fault testing for quasi-delay-insensitive logic circuits. - Arthit Thongtak; Takashi Nanya (Syst. Comput. Jpn., 1998)

A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm. - Elias Procópio Duarte Jr.; Takashi Nanya (IEEE Trans. Computers, 1998)

A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation. - Andreas Savva; Takashi Nanya (IEEE Trans. Computers, 1999)

A testable design for asynchronous fine-grain pipeline circuits. - Masayuki Tsukisaka; Takashi Nanya (PRDC, 2000)

Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. - Hiroto Kagotani; Takuji Okamoto; Takashi Nanya (ASP-DAC, 2001)

Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. - Motokazu Ozawa; Masashi Imai; Hiroshi Nakamura; Takashi Nanya; Yoichiro Ueno (ASYNC, 2001)

Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. - Metehan Özcan; Masashi Imai; Takashi Nanya (ASYNC, 2002)

An equivalence checking methodology for hardware oriented C-based specifications. - Hiroshi Saito; Takaya Ogawa; Thanyapat Sakunkonchak; Masahiro Fujita; Takashi Nanya (HLDVT, 2002)

Logic Optimization for Asynchronous SI Controllers using Transduction Method. - Hiroshi Saito; Hiroshi Nakamura; Masahiro Fujita; Takashi Nanya (IWLS, 2002)

High Throughput Asynchronous Domino Using Dual output Buffer. - Masayuki Tsukisaka; Masashi Imai; Takashi Nanya (IWLS, 2002)

Design of Asynchronous Controllers with Delay Insensitive Interface. - Hiroshi Saito; Alex Kondratyev; Takashi Nanya (ASP-DAC/VLSI Design, 2002)

Design of Asynchronous Controllers with Delay Insensitive Interface. - Hiroshi Saito; Alex Kondratyev; Jordi Cortadella; Luciano Lavagno; Alex Yakovlev; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. - Euiseok Kim; Dong-Ik Lee; Hiroshi Saito; Hiroshi Nakamura; Jeong-Gun Lee; Takashi Nanya (ASP-DAC, 2003)

Logic optimization for asynchronous speed independent controllers using transduction method. - Hiroshi Saito; Hiroshi Nakamura; Masahiro Fujita; Takashi Nanya (ASP-DAC, 2003)

Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. - Hiroshi Saito; Euiseok Kim; Nattha Sretasereekul; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (ASYNC, 2003)

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. - Euiseok Kim; Hiroshi Saito; Jeong-Gun Lee; Dong-Ik Lee; Hiroshi Nakamura; Takashi Nanya (DATE, 2003)

A Reconfigurable High Availability Infrastructure in Cluster for Grid. - Wen Gao 001; Xinyu Liu; Lei Wang 001; Takashi Nanya (GCC (1), 2003)

Control signal sharing of asynchronous circuits using datapath delay information. - Hiroshi Saito; Euiseok Kim; Masashi Imai; Nattha Sretasereekul; Hiroshi Nakamura; Takashi Nanya (ISCAS (5), 2003)

A zero-time-overhead asynchronous four-phase controller. - Nattha Sretasereekul; Hiroshi Saito; Masashi Imai; Euiseok Kim; Metehan Özcan; K. Thongnoo; Hiroshi Nakamura; Takashi Nanya (ISCAS (5), 2003)

Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits. - Nattha Sretasereekul; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. - Nattha Sretasereekul; Hiroshi Saito; Euiseok Kim; Metehan Özcan; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. - Masashi Imai; Metehan Özcan; Takashi Nanya (ASYNC, 2004)

Asynchronous Scan-Latch controller for Low Area Overhead DFT. - Masayuki Tsukisaka; Masashi Imai; Takashi Nanya (ICCD, 2004)

Skewed Checkpointing for Tolerating Multi-Node Failures. - Hiroshi Nakamura; Takuro Hayashida; Masaaki Kondo; Yuya Tajima; Masashi Imai; Takashi Nanya (SRDS, 2004)

Two Cache Replacement Algorithms Based on Association Rules and Markov Models. - Keqiu Li; Wenyu Qu; Hong Shen 001; Di Wu; Takashi Nanya (SKG, 2005)

The Cache Replacement Problem for Multimedia Object Caching. - Wenyu Qu; Keqiu Li; Hong Shen 001; Yingwei Jin; Takashi Nanya (SKG, 2005)

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. - Hiroshi Saito; Nattha Jindapetch; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (CIT, 2006)

A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. - Masashi Imai; Takashi Nanya (ASYNC, 2006)

State-of-Art Techniques for Object Caching over the Internet. - Keqiu Li; Takashi Nanya; Bo Jiang; Wenyu Qu (IMSCCS (2), 2006)

A Scenario of Tolerating Interaction Faults Between Otherwise Correct Systems. - Bogdan Tomoyuki Nassu; Takashi Nanya (PRDC, 2006)

Design Method of High Performance and Low Power Functional Units Considering Delay Variations. - Kouichi Watanabe; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. - Ryo Watanabe; Masaaki Kondo; Masashi Imai; Hiroshi Nakamura; Takashi Nanya (DATE, 2007)

An Efficient Method for Improving Data Collection Precision in Lifetime-adaptive Wireless Sensor Networks. - Wenyu Qu; Keqiu Li; Masaru Kitsuregawa; Takashi Nanya (ICC, 2007)

Power reduction of chip multi-processors using shared resource control cooperating with DVFS. - Ryo Watanabe; Masaaki Kondo; Hiroshi Nakamura; Takashi Nanya (ICCD, 2007)

A Minimal Access Cost-Based Multimedia Object Replacement Algorithm. - Keqiu Li; Takashi Nanya; Wenyu Qu (IPDPS, 2007)

Topology Discovery in Dynamic and Decentralized Networks with Mobile Agents and Swarm Intelligence. - Bogdan Tomoyuki Nassu; Takashi Nanya; Elias P. Duarte Jr. (ISDA, 2007)

Challenges in Dependability of Networked Systems for Information Society. - Takashi Nanya (NPC, 2007)

Energy Efficient Methods and Techniques for Mobile Computing. - Keqiu Li; Takashi Nanya; Wenyu Qu (SKG, 2007)

An optimal solution for caching multimedia objects in transcoding proxies. - Wenyu Qu; Keqiu Li; Masaru Kitsuregawa; Takashi Nanya (Comput. Commun., 2007)

An efficient cache replacement algorithm for multimedia object caching. - Keqiu Li; Takashi Nanya; Hong Shen 001; Francis Y. L. Chin; Weishi Zhang (Comput. Syst. Sci. Eng., 2007)

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. - Hiroshi Saito; Naohiro Hamada; Nattha Jindapetch; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). - Naohiro Hamada; Yuki Shiga; Hiroshi Saito; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (ACSD, 2008)

A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. - Masashi Imai; Takashi Nanya (ACSD, 2008)

Injecting Inconsistent Values Caused by Interaction Faults for Experimental Dependability Evaluation. - Bogdan Tomoyuki Nassu; Kiyonobu Uehara; Takashi Nanya (EDCC, 2008)

Discovering Implicit Redundancies in Network Communications for Detecting Inconsistent Values. - Bogdan Tomoyuki Nassu; Takashi Nanya; Hiroshi Nakamura (ICDM Workshops, 2008)

Interaction Faults Caused by Third-Party External Systems - A Case Study and Challenges. - Bogdan Tomoyuki Nassu; Takashi Nanya (ISAS, 2008)

Limitations of the Linux Fault Injection Framework to Test Direct Memory Access Address Errors. - Roberto Jung Drebes; Takashi Nanya (PRDC, 2008)

Detecting Inconsistent Values Caused by Interaction Faults Using Automatically Located Implicit Redundancies. - Bogdan Tomoyuki Nassu; Takashi Nanya; Hiroshi Nakamura (PRDC, 2008)

Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. - Masashi Imai; Kouei Takada; Takashi Nanya (ASYNC, 2009)

N-way ring and square arbiters. - Masashi Imai; Tomohiro Yoneda; Takashi Nanya (ICCD, 2009)

Zapmem: A Framework for Testing the Effect of Memory Corruption Errors on Operating System Kernel Reliability. - Roberto Jung Drebes; Takashi Nanya (PRDC, 2009)

An optimal lifetime-adaptive method for wireless sensor networks. - Wenyu Qu; Masaru Kitsuregawa; Yanming Shen; Takashi Nanya (Comput. Syst. Sci. Eng., 2009)

A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. - Naohiro Hamada; Yuki Shiga; Takao Konishi; Hiroshi Saito; Tomohiro Yoneda; Chris J. Myers; Takashi Nanya (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. - Masashi Imai; Tomohide Nagai; Takashi Nanya (DSN Workshops, 2010)

Analysis of Inter-Module Error Propagation Paths in Monolithic Operating System Kernels. - Roberto Jung Drebes; Takashi Nanya (EDCC, 2010)

A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. - Hiroshi Saito; Naohiro Hamada; Tomohiro Yoneda; Takashi Nanya (ISCAS, 2010)

An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. - James L. Weston; Masashi Imai; Tomohide Nagai; Takashi Nanya (PRDC, 2010)

Introduction to the fifth workshop on dependable and secure nanocomputing. - Jean Arlat; Cristian Constantinescu; Johan Karlsson; Takashi Nanya; Alan Wood (DSN, 2011)

Nanocomputing: Small Devices, Large Dependability Challenges. - Jean Arlat; Zbigniew Kalbarczyk; Takashi Nanya (IEEE Secur. Priv., 2012)