A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. - Tatsuji Matsuura; Takashi Nara; Tatsuya Komatsu; Eiki Imaizumi; Toshihiro Matsutsuru; Ryutaro Horita; Haruto Katsu; Shintaro Suzumura; Kazuo Sato (IEEE J. Solid State Circuits, 1998)

Turbo decoding of a low-density generator matrix code for a high-density magnetic recording channel. - Takushi Nishiya; Seiichi Mita; Takashi Nara (GLOBECOM, 2000)

An Analysis of Characteristics of Student-Athletes from Questionnaire by SVM. - Toru Sugihara; Soichiro Aihara; Sachio Hirokawa; Takashi Nara (IIAI-AAI, 2017)