Novel via Chain Structure for Failure Analysis at 65 nm-Node Fixing OPC Using Inner and Outer via Chain Dummy Patterns. - Takashi Nasuno; Yoshihisa Matsubara; Hiromasa Kobayashi; Akiyuki Minami; Eiichi Soda; Hiroshi Tsuda; Koichiro Tsujita; Wataru Wakamiya; Nobuyoshi Kobayashi (IEICE Trans. Electron., 2005)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)