250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture. - Yasuhiro Takai; Mamoru Nagase; Mamoru Kitamura; Yasuji Koshikawa; Naoyuki Yoshida; Yasuaki Kobayashi; Takashi Obara; Yukio Fukuzo; Hiroshi Watanabe (IEEE J. Solid State Circuits, 1994)

Exploration of Underwater Volcano Teisi by Autonomous Underwater Vehicle "R-One Robot". - Kenji Nagahashi; Takashi Obara; Tamaki Ura (J. Robotics Mechatronics, 2002)

Automated Habit Detection System: A Feasibility Study. - Hiroki Misawa; Takashi Obara; Hitoshi Iyatomi (ISVC (2), 2015)

Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. - Zhwen Chen; Young-Suk Kim; Tadashi Fukuda; Koji Sakui; Takayuki Ohba; Tatsuji Kobayashi; Takashi Obara (IRPS, 2021)