A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM. - Kazuyuki Nakamura; Takashi Oguri; Takao Atsumo; Masahide Takada; Atsushi Ikemoto; Hisamitsu Suzuki; Tadashi Nishigori; Tohru Yamazaki (IEEE J. Solid State Circuits, 1992)

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. - Hitoshi Okamura; Hideo Toyoshima; Koichi Takeda; Takashi Oguri; Satoshi Nakamura; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Hiroshi Yoshida; Tom Yamazaki (IEEE J. Solid State Circuits, 1995)