A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. - Masato Iwabuchi; Masami Usami; Masamori Kashiyama; Takashi Oomori; Shigeharu Murata; Toshiro Hiramoto; Takashi Hashimoto; Yasuhiro Nakajima (IEEE J. Solid State Circuits, 1994)