An efficient algorithm for layout compaction problem with symmetry constraints. - R. Okuda; Takashi Sato 001; Hidetoshi Onodera; K. Tamariu (ICCAD, 1989)

A 5-GByte/s data-transfer scheme with bit-to-bit skew control for synchronous DRAM. - Takashi Sato 001; Yoji Nishio; Toshio Sugano; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1999)

New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. - Yu Cao 001; Takashi Sato 001; Michael Orshansky; Dennis Sylvester; Chenming Hu (CICC, 2000)

Accurate in situ measurement of peak noise and delay change induced by interconnect coupling. - Takashi Sato 001; Dennis Sylvester; Yu Cao 001; Chenming Hu (IEEE J. Solid State Circuits, 2001)

Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. - Kanak Agarwal 001; Yu Cao 001; Takashi Sato 001; Dennis Sylvester; Chenming Hu (ASP-DAC/VLSI Design, 2002)

Approximate formulae approach for efficient inductance extraction. - Atsushi Kurokawa; Takashi Sato 001; Hiroo Masuda (ASP-DAC, 2003)

Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. - Takashi Sato 001; Toshiki Kanamoto; Atsushi Kurokawa; Yoshiyuki Kawakami; Hiroki Oka; Tomoyasu Kitaura; Hiroyuki Kobayashi; Masanori Hashimoto (ASP-DAC, 2003)

Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. - Takashi Sato 001; Hiroo Masuda (ISQED, 2003)

Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. - Atsushi Kurokawa; Kotaro Hachiya; Takashi Sato 001; Kazuya Tokumasu; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. - Atsushi Kurokawa; Takashi Sato 001; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. - Takashi Sato 001; Yu Cao 001; Kanak Agarwal 001; Dennis Sylvester; Chenming Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Probabilistic crosstalk delay estimation for ASICs. - Kan Takeuchi; Kazumasa Yanagisawa; Takashi Sato 001; Kazuko Sakamoto; Saburo Hojo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. - Takashi Sato 001; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2005)

Successive Pad Assignment for Minimizing Supply Voltage Drop. - Takashi Sato 001; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. - Takashi Sato 001; Junji Ichimiya; Nobuto Ono; Koutaro Hachiya; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Thermal Driven Module Placement Using Sequence-pair. - Norihide Okada; Chikaaki Kodama; Takashi Sato 001; Kunihiro Fujiyoshi (APCCAS, 2006)

Measurement results of delay degradation due to power supply noise well correlated with full-chip simulation. - Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato 001; Takao Onoye (CICC, 2006)

A Time-Slicing Ring Oscillator for Capturing Instantaneous Delay Degradation and Power Supply Voltage Drop. - Takashi Sato 001; Yu Matsumoto; Koji Hirakimoto; Michio Komoda; Junichi Mano (CICC, 2006)

A Method to Derive SSO Design Rule Considering Jitter Constraint. - Koutaro Hachiya; Hiroyuki Kobayashi; Takaaki Okumura; Takashi Sato 001; Hiroki Oka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. - Takashi Sato 001; Junji Ichimiya; Nobuto Ono; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Multi-Drop Transmission-Line Interconnect in Si LSI. - Junki Seita; Hiroyuki Ito; Kenichi Okada 001; Takashi Sato 001; Kazuya Masu (ASP-DAC, 2007)

Improvement of power distribution network using correlation-based regression analysis. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (ACM Great Lakes Symposium on VLSI, 2007)

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. - Takashi Sato 001; Takumi Uezono; Shiho Hagiwara; Kenichi Okada 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu (ISQED, 2007)

Weakness Identification for Effective Repair of Power Distribution Network. - Takashi Sato 001; Shiho Hagiwara; Takumi Uezono; Kazuya Masu (PATMOS, 2007)

Adaptable wire-length distribution with tunable occupation probability. - Shuhei Amakawa; Takumi Uezono; Takashi Sato 001; Kenichi Okada 001; Kazuya Masu (SLIP, 2007)

Proposal of Metrics for SSTA Accuracy Evaluation. - Hiroyuki Kobayashi; Nobuto Ono; Takashi Sato 001; Jiro Iwai; Hidenari Nakashima; Takaaki Okumura; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. - Yasuhiro Ogasahara; Takashi Enami; Masanori Hashimoto; Takashi Sato 001; Takao Onoye (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Determination of optimal polynomial regression function to decompose on-die systematic and random variations. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (ASP-DAC, 2008)

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (DAC, 2008)

Decoupling capacitance allocation for timing with statistical noise model and timing analysis. - Takashi Enami; Masanori Hashimoto; Takashi Sato 001 (ICCAD, 2008)

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Timing Analysis Considering Temporal Supply Voltage Fluctuation. - Masanori Hashimoto; Junji Yamaguchi; Takashi Sato 001; Hidetoshi Onodera (IEICE Trans. Inf. Syst., 2008)

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. - Kenta Yamada; Takashi Sato 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu; Shigetaka Kumashiro (IEICE Trans. Electron., 2008)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato 001; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu (Asian Test Symposium, 2009)

Physical design challenges to nano-CMOS circuits. - Kazuya Masu; Noboru Ishihara; Noriaki Nakayama; Takashi Sato 001; Shuhei Amakawa (IEICE Electron. Express, 2009)

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. - Shiho Hagiwara; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. - Takaaki Okumura; Atsushi Kurokawa; Hiroo Masuda; Toshiki Kanamoto; Masanori Hashimoto; Hiroshi Takafuji; Hidenari Nakashima; Nobuto Ono; Tsuyoshi Sakata; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. - Tsuyoshi Sakata; Takaaki Okumura; Atsushi Kurokawa; Hidenari Nakashima; Hiroo Masuda; Takashi Sato 001; Masanori Hashimoto; Koutaro Hachiya; Katsuhiro Furukawa; Masakazu Tanaka; Hiroshi Takafuji; Toshiki Kanamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

One-Shot Voltage-Measurement Circuit Utilizing Process Variation. - Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. - Koh Yamanaga; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (IEEE J. Solid State Circuits, 2009)

Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. - Kentaro Katayama; Shiho Hagiwara; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ICCAD, 2010)

Decomposition of drain-current variation into gain-factor and threshold voltage variations. - Takashi Sato 001; Takumi Uezono; Noriaki Nakayama; Kazuya Masu (ISCAS, 2010)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

Robust importance sampling for efficient SRAM yield analysis. - Takanori Date; Shiho Hagiwara; Kazuya Masu; Takashi Sato 001 (ISQED, 2010)

Linear time calculation of state-dependent power distribution network capacitance. - Shiho Hagiwara; Koh Yamanaga; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (ISQED, 2010)

Application of generalized scattering matrix for prediction of power supply noise. - Koh Yamanaga; Kazuya Masu; Takashi Sato 001 (SLIP, 2010)

A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (SoCC, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. - Shiho Hagiwara; Koh Yamanaga; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Impact of Self-Heating in Wire Interconnection on Timing. - Toshiki Kanamoto; Takaaki Okumura; Katsuhiro Furukawa; Hiroshi Takafuji; Atsushi Kurokawa; Koutaro Hachiya; Tsuyoshi Sakata; Masakazu Tanaka; Hidenari Nakashima; Hiroo Masuda; Takashi Sato 001; Masanori Hashimoto (IEICE Trans. Electron., 2010)

A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. - Takashi Sato 001; Toshiki Kanamoto; Saiko Kobayashi; Nobuhiko Goto; Takao Sato; Hitoshi Sugihara; Hiroo Masuda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. - Takumi Uezono; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2010)

A Universal Equivalent Circuit Model for Ceramic Capacitors. - Koh Yamanaga; Shuhei Amakawa; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2010)

Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. - Zhangcai Huang; Atsushi Kurokawa; Masanori Hashimoto; Takashi Sato 001; Minglu Jiang; Yasuaki Inoue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Acceleration of random-walk-based linear circuit analysis using importance sampling. - Tetsuro Miyakawa; Koh Yamanaga; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2011)

A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. - Hiroshi Yuasa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2011)

A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. - Junya Kawashima; Hiroyuki Ochi; Hiroshi Tsutsui; Takashi Sato 001 (SoCC, 2011)

Statistical aging under dynamic voltage scaling: A logarithmic model approach. - Jyothi Velamala; Ketul Sutaria; Hirofumi Shimizu; Hiromitsu Awano; Takashi Sato 001; Yu Cao 001 (CICC, 2012)

Physics matters: statistical aging prediction under trapping/detrapping. - Jyothi Bhaskarr Velamala; Ketul Sutaria; Takashi Sato 001; Yu Cao 001 (DAC, 2012)

Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. - Takashi Sato 001; Hiromitsu Awano; Hirofttmi Shimizu; Hiroshi Tsutsui; Hiroyuki Ochi (ISQED, 2012)

A Bayesian-based process parameter estimation using IDDQ current signature. - Michihiro Shintani; Takashi Sato 001 (VTS, 2012)

Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. - Takashi Enami; Takashi Sato 001; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. - Junya Kawashima; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Statistical simulation methods for circuit performance analysis. - Takashi Sato 001 (ASICON, 2013)

Realization of frequency-domain circuit analysis through random walk. - Tetsuro Miyakawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ASP-DAC, 2013)

An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. - Michihiro Shintani; Takashi Sato 001 (ASP-DAC, 2013)

A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (DATE, 2013)

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. - Zoltán Endre Rákossy; Masayuki Hiromoto; Hiroshi Tsutsui; Takashi Sato 001; Yukihiro Nakamura; Hiroyuki Ochi (DATE, 2013)

Fast and memory-efficient GPU implementations of krylov subspace methods for efficient power grid analysis. - Takumi Morishita; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2013)

Multi-trap RTN parameter extraction based on Bayesian inference. - Hiromitsu Awano; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

High-speed DFG-level SEU vulnerability analysis for applying selective TMR to resource-constrained CGRA. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (ISQED, 2013)

A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. - Takashi Imagawa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2013)

Device-Parameter Estimation through IDDQ Signatures. - Michihiro Shintani; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2013)

Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. - Hiroshi Yuasa; Hiroshi Tsutsui; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2013)

Variability in device degradations: Statistical observation of NBTI for 3996 transistors. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ESSDERC, 2014)

Sensorless estimation of global device-parameters based on Fmax testing. - Michihiro Shintani; Takashi Sato 001 (ICCAD, 2014)

Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. - Takashi Sato 001; Junya Kawashima; Hiroshi Tsutsui; Hiroyuki Ochi (ISQED, 2014)

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. - Shiho Hagiwara; Takanori Date; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2014)

Automation of Model Parameter Estimation for Random Telegraph Noise. - Hirofumi Shimizu; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. - Michihiro Shintani; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2014)

State-Dependence of On-Chip Power Distribution Network Capacitance. - Koh Yamanaga; Shiho Hagiwara; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2014)

A Variability-Aware Adaptive Test Flow for Test Quality Improvement. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

ECRIPSE: an efficient method for calculating RTN-induced failure probability of an SRAM cell. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2015)

An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs. - Takashi Imagawa; Masayuki Hiromoto; Hiroyuki Ochi; Takashi Sato 001 (IEICE Trans. Electron., 2015)

Introduction to: Special Issue on Cross-Layer System Design. - Yiyu Shi 001; Takashi Sato 001 (ACM J. Emerg. Technol. Comput. Syst., 2015)

Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. - Song Bian 001; Michihiro Shintani; Zheng Wang 020; Masayuki Hiromoto; Anupam Chattopadhyay; Takashi Sato 001 (ATS, 2016)

Approximated Prediction Strategy for Reducing Power Consumption of Convolutional Neural Network Processor. - Takayuki Ujiie; Masayuki Hiromoto; Takashi Sato 001 (CVPR Workshops, 2016)

Efficient transistor-level timing yield estimation via line sampling. - Hiromitsu Awano; Takashi Sato 001 (DAC, 2016)

Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ACM Great Lakes Symposium on VLSI, 2016)

Physically unclonable function using RTN-induced delay fluctuation in ring oscillators. - Motoki Yoshinaga; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ISCAS, 2016)

Nonlinear delay-table approach for full-chip NBTI degradation prediction. - Song Bian 001; Michihiro Shintani; Shumpei Morita; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2016)

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. - Michihiro Shintani; Takumi Uezono; Kazumi Hatayama; Kazuya Masu; Takashi Sato 001 (J. Electron. Test., 2016)

Efficient Aging-Aware SRAM Failure Probability Calculation via Particle Filter-Based Importance Sampling. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Efficient circuit failure probability calculation along product lifetime considering device aging. - Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2017)

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. - Yu-Guang Chen; Michihiro Shintani; Takashi Sato 001; Yiyu Shi 001; Shih-Chieh Chang (ASP-DAC, 2017)

LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. - Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2017)

SCAM: Secured content addressable memory based on homomorphic encryption. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2017)

Comparative study of path selection and objective function in replacing NBTI mitigation logic. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2017)

Efficient Aging-Aware Failure Probability Estimation Using Augmented Reliability and Subset Simulation. - Hiromitsu Awano; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Identification and Application of Invariant Critical Paths under NBTI Degradation. - Song Bian 001; Shumpei Morita; Michihiro Shintani; Hiromitsu Awano; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Scalable Device Array for Statistical Characterization of BTI-Related Parameters. - Hiromitsu Awano; Shumpei Morita; Takashi Sato 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

RTN in Scaled Transistors for On-Chip Random Seed Generation. - Abinash Mohanty; Ketul B. Sutaria; Hiromitsu Awano; Takashi Sato 001; Yu Cao 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2018)

Interpolation-Based Object Detection Using Motion Vectors for Embedded Real-Time Tracking Systems. - Takayuki Ujiie; Masayuki Hiromoto; Takashi Sato 001 (CVPR Workshops, 2018)

DWE: decrypting learning with errors with errors. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2018)

Ising-PUF: A machine learning attack resistant PUF featuring lattice like arrangement of Arbiter-PUFs. - Hiromitsu Awano; Takashi Sato 001 (DATE, 2018)

Fast And Robust Heart Rate Estimation From Videos Through Dynamic Region Selection. - Yuya Fujita; Masayuki Hiromoto; Takashi Sato 001 (EMBC, 2018)

Enhancing the solution quality of hardware ising-model solver via parallel tempering. - Hidenori Gyoten; Masayuki Hiromoto; Takashi Sato 001 (ICCAD, 2018)

A study on NBTI-induced delay degradation considering stress frequency dependence. - Zuitoku Shin; Shumpei Morita; Song Bian 001; Michihiro Shintani; Masayuki Hiromoto; Takashi Sato 001 (ISQED, 2018)

Area Efficient Annealing Processor for Ising Model without Random Number Generator. - Hidenori Gyoten; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Inf. Syst., 2018)

MRO-PUF: Physically Unclonable Function with Enhanced Resistance against Machine Learning Attacks Utilizing Instantaneous Output of Ring Oscillator. - Masayuki Hiromoto; Motoki Yoshinaga; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Efficient Mini-Batch Training on Memristor Neural Network Integrating Gradient Calculation and Weight Update. - Satoshi Yamamori; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

PARHELIA: Particle Filter-Based Heart Rate Estimation From Photoplethysmographic Signals During Physical Exercise. - Yuya Fujita; Masayuki Hiromoto; Takashi Sato 001 (IEEE Trans. Biomed. Eng., 2018)

Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks. - Yuki Tanaka; Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (ASP-DAC, 2019)

Heart Rate Estimation during Exercise from Photoplethysmographic Signals Using Convolutional Neural Network. - Masaki Nakamura; Takashi Sato 001 (BioCAS, 2019)

Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key Exchange. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DAC, 2019)

DArL: Dynamic Parameter Adjustment for LWE-based Secure Inference. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (DATE, 2019)

Hardware-Accelerated Secured Naïve Bayesian Filter Based on Partially Homomorphic Encryption. - Song Bian 001; Masayuki Hiromoto; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

GPU-based Ising computing for solving max-cut combinatorial optimization problems. - Chase Cook; Hengyang Zhao; Takashi Sato 001; Masayuki Hiromoto; Sheldon X.-D. Tan (Integr., 2019)

A Tuning-Free Hardware Reservoir Based on MOSFET Crossbar Array for Practical Echo State Network Implementation. - Yuki Kume; Song Bian 001; Takashi Sato 001 (ASP-DAC, 2020)

Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. - Yohei Nakamura; Naotaka Kuroda; Atsushi Yamaguchi; Ken Nakahara; Michihiro Shintani; Takashi Sato 001 (ATS, 2020)

Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. - Aoi Ueda; Michihiro Shintani; Michiko Inoue; Takashi Sato 001 (ATS, 2020)

ENSEI: Efficient Secure Inference via Frequency-Domain Homomorphic Convolution for Privacy-Preserving Visual Recognition. - Song Bian 001; Tianchen Wang; Masayuki Hiromoto; Yiyu Shi 001; Takashi Sato 001 (CVPR, 2020)

Clustering Approach for Solving Traveling Salesman Problems via Ising Model Based Solver. - Akira Dan; Riu Shimizu; Takeshi Nishikawa; Song Bian 001; Takashi Sato 001 (DAC, 2020)

NASS: Optimizing Secure Inference via Neural Architecture Search. - Song Bian 001; Weiwen Jiang; Qing Lu 001; Yiyu Shi 001; Takashi Sato 001 (ECAI, 2020)

BUNET: Blind Medical Image Segmentation Based on Secure UNET. - Song Bian 001; Xiaowei Xu 004; Weiwen Jiang; Yiyu Shi 001; Takashi Sato 001 (MICCAI (2), 2020)

FedNNNN: Norm-Normalized Neural Network Aggregation for Fast and Accurate Federated Learning. - Kenta Nagura; Song Bian 001; Takashi Sato 001 (CoRR, 2020)

Ed-PUF: Event-Driven Physical Unclonable Function for Camera Authentication in Reactive Monitoring System. - Yue Zheng; Xiaojin Zhao; Takashi Sato 001; Yuan Cao 003; Chip-Hong Chang (IEEE Trans. Inf. Forensics Secur., 2020)

Heart Rate Variability Extraction using Commodity Wi-Fi Devices via Time Domain Signal Processing. - Itsuki Shirakami; Takashi Sato 001 (BHI, 2021)

Motion Robust Remote Photoplethysmography via Frequency Domain Motion Artifact Reduction. - Suraj Hebbar; Takashi Sato 001 (BioCAS, 2021)

Towards Better Standard Cell Library: Optimizing Compound Logic Gates for TFHE. - Kotaro Matsuoka; Yusuke Hoshizuki; Takashi Sato 001; Song Bian 001 (WAHC@CCS, 2021)

Privacy-Preserving Medical Image Segmentation via Hybrid Trusted Execution Environment. - Song Bian 001; Weiwen Jiang; Takashi Sato 001 (DAC, 2021)

Overview of 2021 CAD Contest at ICCAD. - Tsung-Wei Huang; Yu-Guang Chen; Chun-Yao Wang; Takashi Sato 001 (ICCAD, 2021)

Virtual Secure Platform: A Five-Stage Pipeline Processor over TFHE. - Kotaro Matsuoka; Ryotaro Banno; Naoki Matsumoto; Takashi Sato 001; Song Bian 001 (USENIX Security Symposium, 2021)

Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. - Michihiro Shintani; Aoi Ueda; Takashi Sato 001 (CoRR, 2021)

Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. - Tatsuki Ono; Song Bian 001; Takashi Sato 001 (IACR Cryptol. ePrint Arch., 2021)

Clonable PUF: On the Design of PUFs That Share Equivalent Responses. - Takashi Sato 001; Yuki Tanaka; Song Bian 001 (IACR Cryptol. ePrint Arch., 2021)

APAS: Application-Specific Accelerators for RLWE-Based Homomorphic Linear Transformations. - Song Bian 001; Dur-e-Shahwar Kundi; Kazuma Hirozawa; Weiqiang Liu 001; Takashi Sato 001 (IEEE Trans. Inf. Forensics Secur., 2021)

Respiratory Rate Estimation Based on WiFi Frame Capture. - Takamochi Kanda; Takashi Sato 001; Hiromitsu Awano; Sota Kondo; Koji Yamamoto 001 (CCNC, 2022)

Overview of 2022 CAD Contest at ICCAD. - Yu-Guang Chen; Chun-Yao Wang; Tsung-Wei Huang; Takashi Sato 001 (ICCAD, 2022)

Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Their Recovery. - Masato Shiozaki; Takashi Sato 001 (IRPS, 2022)

Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. - Kyohei Shimozato; Michihiro Shintani; Takashi Sato 001 (CoRR, 2022)

VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. - Tianchen Wang; Jiawei Zhang; Jinjun Xiong; Song Bian 001; Zheyu Yan; Meiping Huang; Jian Zhuang; Takashi Sato 001; Xiaowei Xu 004; Yiyu Shi 001 (IEEE Trans. Computers, 2022)

Hardware-Friendly Delayed-Feedback Reservoir for Multivariate Time-Series Classification. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. - Shumpei Morita; Song Bian 001; Michihiro Shintani; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Invited Paper: Overview of 2023 CAD Contest at ICCAD. - Takashi Sato 001; Chun-Yao Wang; Yu-Guang Chen; Tsung-Wei Huang (ICCAD, 2023)

Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. - Makoto Eiki; Tomoki Nakamura; Masuo Kajiyama; Michiko Inoue; Takashi Sato 001; Michihiro Shintani (ITC, 2023)

Uncertainty-Aware Haptic Shared Control With Humanoid Robots for Flexible Object Manipulation. - Takumi Hara; Takashi Sato 001; Tetsuya Ogata; Hiromitsu Awano (IEEE Robotics Autom. Lett., 2023)

Modular DFR: Digital Delayed Feedback Reservoir Model for Enhancing Design Flexibility. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (ACM Trans. Embed. Comput. Syst., 2023)

HOGE: Homomorphic Gate on An FPGA. - Kotaro Matsuoka; Song Bian 001; Takashi Sato 001 (ASPDAC, 2024)

Logic Locking over TFHE for Securing User Data and Algorithms. - Kohei Suemitsu; Kotaro Matsuoka; Takashi Sato 001; Masanori Hashimoto (ASPDAC, 2024)

Triplet Network-Based DNA Encoding for Enhanced Similarity Image Retrieval. - Takefumi Koike; Hiromitsu Awano; Takashi Sato 001 (DAC, 2024)

Fast Parameter Optimization of Delayed Feedback Reservoir with Backpropagation and Gradient Descent. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (DATE, 2024)

DNA-Based Similar Image Retrieval via Triplet Network-Driven Encoder. - Takefumi Koike; Hiromitsu Awano; Takashi Sato 001 (DATE, 2024)

(Invited) Redefining Outliers for On-Wafer Electrical Testing. - Michihiro Shintani; Takashi Sato 001 (MLCAD, 2024)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. - Ryosuke Matsuo; Kazuhisa Ogawa; Hidehisa Shiorni; Makoto Negoro; Ryutaco Ohira; Takefumi Miyoshi; Michihiro Shintani; Hiromitsu Awano; Takashi Sato 001; Jun Shiomi (QCE, 2024)

Exploring Surface Code Decoding via Cryo-CMOS for Fault-Tolerant Quantum Computers. - Ruotai Wang; Takashi Sato 001; Hiromitsu Awano (QCE, 2024)

Double MAC on a Cell: A 22-nm 8T-SRAM-Based Analog In-Memory Accelerator for Binary/Ternary Neural Networks Featuring Split Wordline. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (IEEE Open J. Circuits Syst., 2024)

Cryo-Compact Modeling Based on Sparse Gaussian Process. - Tetsuro Iwasaki; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K. - Takuma Kawakami; Takashi Sato 001; Hiromitsu Awano (ASP-DAC, 2025)

Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. - Dondee Navarro; Shin Taniguchi; Chika Tanaka; Kazutoshi Kobayashi; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. - Quan Cheng; Qiufeng Li; Weirong Dong; Mingtao Zhang; Ruilin Zhang; Mingqiang Huang; Hao Yu 001; Yiyu Shi 001; Hiromitsu Awano; Takashi Sato 001; Longyang Lin; Masanori Hashimoto (CICC, 2025)

Zero-Aware Regularization for Energy-Efficient Inference on Akida Neuromorphic Processor. - Takehiro Habara; Takashi Sato 001; Hiromitsu Awano (ISCAS, 2025)

Gaitcloud: Leveraging Spatial-Temporal Information for Lidar-Base Gait Recognition With a True-3D Gait Representation. - Shaoxiong Zhang; Hiromitsu Awano; Takashi Sato 001 (WACV, 2025)

Beamforming Feedback-Based Respiration and Heart Rate Estimation Toward Firmware-Agnostic WiFi Sensing. - Takamochi Kanda; Sota Kondo; Hiroki Shimomura; Takashi Sato 001; Hiromitsu Awano; Koji Yamamoto 001 (IEEE Access, 2025)

Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline Accumulation. - Hiroto Tagata; Takashi Sato 001; Hiromitsu Awano (CoRR, 2025)

SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. - Xinyi Guo; Geguang Miao; Shinichi Nishizawa; Hiromitsu Awano; Shinji Kimura; Takashi Sato 001 (CoRR, 2025)

Online Training and Inference System on Edge FPGA Using Delayed Feedback Reservoir. - Sosei Ikeda; Hiromitsu Awano; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)