Resolution independent rendering of deformable vector objects using graphics hardware. - Yoshiyuki Kokojima; Kaoru Sugita; Takahiro Saito; Takashi Takemoto (SIGGRAPH Sketches, 2006)

MOSFET implementation of class I* neurons coupled by gap junctions. - Takashi Takemoto; Takashi Kohno; Kazuyuki Aihara (Artif. Life Robotics, 2006)

Circuit Implementation and Dynamics of a Two-Dimensional MOSFET Neuron Model. - Takashi Takemoto; Takashi Kohno; Kazuyuki Aihara (Int. J. Bifurc. Chaos, 2007)

An 8Gb/s Transceiver with 3×-Oversampling 2-Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Masayoshi Yagyu; Ryo Nemoto; Takashi Takemoto; Tatsuya Saito; Norio Chujo; Keiichi Yamamoto; Hisaaki Kanai; Atsuhiro Hayashi (ISSCC, 2008)

10Gb/s receiver with track-and-hold-type linear phase detector and charge-redistribution 1st-order ΔΣ modulator. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Tatsuya Saito (ISSCC, 2009)

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS. - Koji Fukuda; Hiroki Yamashita; Fumio Yuki; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Masashi Kono; Tatsuya Saito (IEEE J. Solid State Circuits, 2009)

A 25 Gb/s × 4-channel 74 mW/ch transimpedance amplifier in 65 nm CMOS. - Takashi Takemoto; Fumio Yuki; Hiroki Yamashita; Shinji Tsuji; Tatsuya Saito; Shinji Nishimura (CICC, 2010)

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (ISSCC, 2010)

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process. - Koji Fukuda; Hiroki Yamashita; Goichi Ono; Ryo Nemoto; Eiichi Suzuki; Noboru Masuda; Takashi Takemoto; Fumio Yuki; Tatsuya Saito (IEEE J. Solid State Circuits, 2010)

10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (ISSCC, 2011)

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. - Goichi Ono; Keiki Watanabe; Takashi Muto; Hiroki Yamashita; Koji Fukuda; Noboru Masuda; Ryo Nemoto; Eiichi Suzuki; Takashi Takemoto; Fumio Yuki; Masayoshi Yagyu; Hidehiro Toyoda; et al. (IEEE J. Solid State Circuits, 2011)

A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. - Takashi Takemoto; Hiroki Yamashita; Takehito Kamimura; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Kenji Kogo; Yong Lee; Shinji Tsuji; Shinji Nishimura (VLSIC, 2012)

Optical Interconnects for Green Computers and Data Centers. - Shinji Tsuji; Takashi Takemoto (Adv. Comput., 2012)

High-frequency circuit design for 25 Gb/s×4 optical transceiver. - Norio Chujo; Takashi Takemoto; Fumio Yuki; Hiroki Yamashita (ASP-DAC, 2013)

A 4× 25-to-28Gb/s 4.9mW/Gb/s -9.7dBm high-sensitivity optical receiver based on 65nm CMOS for board-to-board interconnects. - Takashi Takemoto; Hiroki Yamashita; Toru Yazaki; Norio Chujo; Yong Lee; Yasunobu Matsuoka (ISSCC, 2013)

A 25-Gb/s × 4-Ch, 8 × 8 mm2, 2.8-mm thick compact optical transceiver module for on-board optical interconnect. - Norio Chujo; Toru Yazaki; Toshiaki Takai; Daichi Kawamura; Yasunobu Matsuoka; Yong Lee; Toshiki Sugawara; Hiroki Yamashita; Takashi Takemoto; Yoshiaki Ishigami; Kinya Yamazaki; Yoshinori Sunaga; et al. (OFC/NFOEC, 2013)

Compact and power-efficient 100-Gbps CMOS-based transceiver. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Shinji Tsuji; Yong Lee; Koichiro Adachi; Kazunori Shinoda; Yasunobu Matsuoka; Toshiki Sugawara; Shinji Nishimura; Norio Chujo; Masaaki Nido; et al. (OFC/NFOEC, 2013)

25-Gbps×4 optical transmitter with adjustable asymmetric pre-emphasis in 65-nm CMOS. - Toru Yazaki; Norio Chujo; Hiroki Yamashita; Takashi Takemoto; Yong Lee; Yasunobu Matsuoka (ISCAS, 2014)

A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects. - Takashi Takemoto; Hiroki Yamashita; Toru Yazaki; Norio Chujo; Yong Lee; Yasunobu Matsuoka (IEEE J. Solid State Circuits, 2014)

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. - Takashi Takemoto; Hiroki Yamashita; Fumio Yuki; Noboru Masuda; Hidehiro Toyoda; Norio Chujo; Yong Lee; Shinji Tsuji; Shinji Nishimura (IEEE J. Solid State Circuits, 2014)

An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. - Takashi Takemoto; Hiroki Yamashita; Yasunobu Matsuoka; Yong Lee; Masaru Kokubo (CICC, 2015)

Wide-temperature-range 103.2 (25.8 × 4)-Gb/s optical link for data-center Interconnects using a 1.3-µm lens-integrated surface-emitting laser array. - Koichiro Adachi; Yasunobu Matsuoka; Takashi Takemoto; Takanori Suzuki; Shigehisa Tanaka; Akira Nakanishi; Kazuhiko Naoe (OFC, 2015)

A 50-Gb/s NRZ-modulated optical transmitter based on a DFB-LD and a 0.18-µm SiGe BiCMOS LD driver. - Takashi Takemoto; Yasunobu Matsuoka; Yoshikazu Sugiyama; Hidenori Yonezawa; Hiroki Yamashita; Koichiro Adachi; Takahiro Nakamura; Etsuko Nomoto; Kouji Nakahara; Hideo Arimoto; Kenichi Osada; Tatemi Ido (OFC, 2015)

A jitter-reduction packaging structure for a 56-Gb/s NRZ modulated optical receiver. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Kenichi Akita; Hideo Arimoto; Masaru Kokubo (OFC, 2016)

A 50.6-Gb/s 7.8-mW/Gb/s -7.4-dBm sensitivity optical receiver based on 0.18-µm SiGe BiCMOS technology. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Kenichi Akita; Hideo Arimoto; Masaru Kokubo; Tatemi Ido (VLSI Circuits, 2016)

A 50-Gb/s Optical Transmitter Based on a 25-Gb/s-Class DFB-LD and a 0.18-µm SiGe BiCMOS LD Driver. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Takahiro Nakamura; Yong Lee; Hideo Arimoto; Tatemi Ido (IEICE Trans. Electron., 2016)

FPGA-Based QBoost with Large-Scale Annealing Processor and Accelerated Hyperparameter Search. - Takashi Takemoto; Normann Mertig; Masato Hayashi; Saki Susa-Tanaka; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Tamiki Komatsuzaki; Masanao Yamaoka (ReConFig, 2018)

Graph Minors from Simulated Annealing for Annealing Machines with Sparse Connectivity. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (TPNC, 2018)

A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-µm SiGe BiCMOS Technology. - Takashi Takemoto; Yasunobu Matsuoka; Hiroki Yamashita; Yong Lee; Hideo Arimoto; Masaru Kokubo; Tatemi Ido (IEEE J. Solid State Circuits, 2018)

CMOS Annealing Machine: an In-memory Computing Accelerator to Process Combinatorial Optimization Problems. - Masanao Yamaoka; Takuya Okuyama; Masato Hayashi; Chihiro Yoshimura; Takashi Takemoto (CICC, 2019)

A 2 ×30k-Spin Multichip Scalable Annealing Processor Based on a Processing-In-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Masato Hayashi; Chihiro Yoshimura; Masanao Yamaoka (ISSCC, 2019)

A Cloud-ready Scalable Annealing Processor for Solving Large-scale Combinatorial Optimization Problems. - Masato Hayashi; Takashi Takemoto; Chihiro Yoshimura; Masanao Yamaoka (VLSI Circuits, 2019)

CMOS Annealing Machine: A Domain-Specific Architecture for Combinatorial Optimization Problem. - Chihiro Yoshimura; Masato Hayashi; Takashi Takemoto; Masanao Yamaoka (ASP-DAC, 2020)

7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. - Kasho Yamamoto; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (ISSCC, 2020)

A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Masato Hayashi; Chihiro Yoshimura; Masanao Yamaoka (IEEE J. Solid State Circuits, 2020)

A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems. - Kasho Yamamoto; Takashi Takemoto; Chihiro Yoshimura; Mayumi Mashimo; Masanao Yamaoka (A-SSCC, 2021)

4.6 A 144Kb Annealing System Composed of 9× 16Kb Annealing Processor Chips with Scalable Chip-to-Chip Connections for Large-Scale Combinatorial Optimization Problems. - Takashi Takemoto; Kasho Yamamoto; Chihiro Yoshimura; Masato Hayashi; Masafumi Tada; Hiroaki Saito; Mayumi Mashimo; Masanao Yamaoka (ISSCC, 2021)

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. - Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEEE J. Solid State Circuits, 2021)

Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes. - Yuya Sugie; Yuki Yoshida; Normann Mertig; Takashi Takemoto; Hiroshi Teramoto; Atsuyoshi Nakamura; Ichigaku Takigawa; Shin-ichi Minato; Masanao Yamaoka; Tamiki Komatsuzaki (Soft Comput., 2021)

A Monte Carlo Tree Search for Budget-Constrained Combinatorial Optimal Facility Investment Problem with a Blackbox Objective Function. - Shoma Nameki; Atsuyoshi Nakamura; Yusuke Yasugahira; Hiroshi Uchigaito; Michiaki Hiramatsu; Takashi Takemoto (IEEE Big Data, 2024)