A Low-Power Dual-Band Triple-Mode WLAN CMOS Transceiver. - Tadashi Maeda; Noriaki Matsuno; Shinichi Hori; Tomoyuki Yamase; Takashi Tokairin; Kiyoshi Yanagisawa; Hitoshi Yano; Robert Walkington; Keiichi Numata; Nobuhide Yoshida; Yuji Takahashi; Hikaru Hida (IEEE J. Solid State Circuits, 2006)

Low-power-consumption direct-conversion CMOS transceiver for multi-standard 5-GHz wireless LAN systems with channel bandwidths of 5-20 MHz. - Tadashi Maeda; Hitoshi Yano; Shinichi Hori; Noriaki Matsuno; Tomoyuki Yamase; Takashi Tokairin; Robert Walkington; Nobuhide Yoshida; Keiichi Numata; Kiyoshi Yanagisawa; Yuji Takahashi; Masahiro Fujii; et al. (IEEE J. Solid State Circuits, 2006)

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (ISSCC, 2010)

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2010)

Analytical Expression of Quantization Noise in Time-to-Digital Converter Based on the Fourier Series Analysis. - Tadashi Maeda; Takashi Tokairin (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme. - Masaki Kitsunezuka; Takashi Tokairin; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2011)

A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. - Takashi Tokairin; Koichi Nose; Koichi Takeda 001; Koichiro Noguchi; Tadashi Maeda; Kazuyoshi Kawai; Masayuki Mizuno (VLSIC, 2012)

A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy. - Masayoshi Oshiro; Tatsuhiko Maruyama; Takashi Tokairin; Yuki Tuda; Tong Wang 018; Naotaka Koide; Yosuke Ogasawara; Tuan Thanh Ta; Hiroshi Yoshida; Kenichi Sami (A-SSCC, 2016)

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. - Hidenori Okuni; Akihide Sai; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (ISSCC, 2016)

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. - Akihide Sai; Hidenori Okuni; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (IEEE J. Solid State Circuits, 2016)

A 3.2mA-RX 3.5mA-TX Fully Integrated SoC for Bluetooth Low Energy System. - Masayoshi Oshiro; Tatsuhiko Maruyama; Takashi Tokairin; Yuki Tuda; Tong Wang 018; Naotaka Koide; Yosuke Ogasawara; Tuan Thanh Ta; Hiroshi Yoshida; Kenichi Sami (IEICE Trans. Electron., 2017)

A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX. - Tuan Thanh Ta; Yosuke Ogasawara; Tong Wang 018; Masayoshi Oshiro; Naotaka Koide; Akihide Sai; Takashi Tokairin (ESSCIRC, 2018)

An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX. - Tong Wang 018; Yosuke Ogasawara; Yuki Tuda; Tuan Thanh Ta; Masayoshi Oshiro; Jun Ihara; Tatsuhiko Maruyama; Toru Hashimoto; Akihide Sai; Takashi Tokairin (VLSI Circuits, 2018)