A 46-ns 1-Mbit CMOS SRAM. - Hiroshi Shimada; Shoichiro Kawashima; Hideo Itoh; Noriyuki Suzuki; Takashi Yabu (IEEE J. Solid State Circuits, 1988)

A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. - Masao Taguchi; Hiroyoshi Tomita; Toshiya Uchida; Yasuhiro Ohnishi; Kimiaki Sato; Taiji Ema; Masaaki Higashitani; Takashi Yabu (IEEE J. Solid State Circuits, 1991)