CMOS inverter delay and other formulas using alpha -power law MOS model. - Takayasu Sakurai (ICCAD, 1988)

A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Katsuhiko Sato; Tsukasa Shirotori; Masakazu Kakuma; Shigeru Morita; Masaaki Kinugawa; Tetsuya Asami; Kazuhito Narita; Jun-Ichi Matsunaga; Akira Higuchi; et al. (IEEE J. Solid State Circuits, 1988)

Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFETs. - Takayasu Sakurai (IEEE J. Solid State Circuits, 1988)

A 32 kbyte integrated cache memory. - Kazuhiro Sawada; Takayasu Sakurai; Kazutaka Nogami; Tsukasa Shirotori; Toshinari Takayanagi; Tetsuya Iizuka; Takeo Maeda; Jinichi Matsunaga; Hiromichi Fuji; Kenji Maeguchi; Kiyoshi Kobayashi; Tomoyuki Ando; et al. (IEEE J. Solid State Circuits, 1989)

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. - Kazutaka Nogami; Takayasu Sakurai; Kazuhiro Sawada; Kenji Sakaue; Yuichi Miyazawa; Shinichi Tanaka; Ypocjo Hiruta; Katsuto Katoh; Toshinari Takayanagi; Tsukasa Shirotori; Yasuo Itoh; Masanori Uchida; et al. (IEEE J. Solid State Circuits, 1990)

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas. - Takayasu Sakurai; A. Richard Newton (IEEE J. Solid State Circuits, 1990)

Delay analysis of series-connected MOSFET circuits. - Takayasu Sakurai; A. Richard Newton (IEEE J. Solid State Circuits, 1991)

0.5- mu m 2 M-transistor BiPNMOS channelless gate array. - Hiroyuki Hara; Takayasu Sakurai; Makoto Noda; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Yoshinori Watanabe (IEEE J. Solid State Circuits, 1991)

Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. - Takayasu Sakurai; Bill Lin 001; A. Richard Newton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A unified theory for mixed CMOS/BiCMOS buffer optimization. - Takayasu Sakurai (IEEE J. Solid State Circuits, 1992)

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file. - Hiroyuki Hara; Takayasu Sakurai; Tetsu Nagamatsu; Katsuhiro Seta; Hiroshi Momose; Yoichirou Niitsu; Hiroyuki Miyakawa; Kouji Matsuda; Yoshinori Watanabe; Fumihiko Sano; Akihiko Chiba (IEEE J. Solid State Circuits, 1992)

High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. - Takayasu Sakurai (ISCAS, 1993)

A 110-MHz/1-Mb synchronous TagRAM. - Yasuo Unekawa; Tsuguo Kobayashi; Tsukasa Shirotori; Yukihiro Fujimoto; Takayoshi Shimazawa; Kazutaka Nogami; Takehiko Nakao; Kazukiro Sawada; Masataka Matsui; Takayasu Sakurai; Man Kit Tang; William A. Huffman (IEEE J. Solid State Circuits, 1994)

A 200 MHz 13 mm2 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme. - Masataka Matsui; Hiroyuki Hara; Yoshiharu Uetani; Lee-Sup Kim; Tetsu Nagamatsu; Yoshinori Watanabe; Akihiko Chiba; Kouji Matsuda; Takayasu Sakurai (IEEE J. Solid State Circuits, 1994)

Substrate noise influence on circuit performance in variable threshold-voltage scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Toshiaki Mori; Kenji Matsuo; Masakazu Kakumu; Takayasu Sakurai (ISLPED, 1996)

A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. - Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakurnu; et al. (IEEE J. Solid State Circuits, 1996)

A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications. - Akilesh Parameswar; Hiroyuki Hara; Takayasu Sakurai (IEEE J. Solid State Circuits, 1996)

Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. - Tadahiro Kuroda; Takayasu Sakurai (J. VLSI Signal Process., 1996)

Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. - Hiroshi Kawaguchi 001; Takayasu Sakurai (ASP-DAC, 1998)

Integrated Current Sensing Device for Micro IDDQ Test. - Koichi Nose; Takayasu Sakurai (Asian Test Symposium, 1998)

A fine-grain, current mode scheme for VLSI proximity search engine. - Seiji Takeuchi; Takayasu Sakurai (ICCD, 1998)

A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. - Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE J. Solid State Circuits, 1998)

Variable supply-voltage scheme for low-power high-speed CMOS digital design. - Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama (IEEE J. Solid State Circuits, 1998)

Compact yet high performance (CyHP) library for short time-to-market with new technologies. - Nguyen Minh Duc; Takayasu Sakurai (ASP-DAC, 2000)

Run-time power control scheme using software feedback loop for low-power real-time application. - Seongsoo Lee; Takayasu Sakurai (ASP-DAC, 2000)

Optimization of VDD and VTH for low-power and high speed applications. - Koichi Nose; Takayasu Sakurai (ASP-DAC, 2000)

Design challenges for 0.1um and beyond: embedded tutorial. - Takayasu Sakurai (ASP-DAC, 2000)

Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. - Takashi Inukai; Makoto Takamiya; Kouichi Nose; Hiroshi Kawaguchi 001; Toshiro Hiramoto; Takayasu Sakurai (CICC, 2000)

Run-time voltage hopping for low-power real-time systems. - Seongsoo Lee; Takayasu Sakurai (DAC, 2000)

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (ICCAD, 2000)

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). - Koichi Nose; Soo-Ik Chae; Takayasu Sakurai (ISLPED, 2000)

Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. - Takayasu Sakurai (ISQED, 2000)

A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. - Hiroshi Kawaguchi 001; Koichi Nose; Takayasu Sakurai (IEEE J. Solid State Circuits, 2000)

Analysis and future trend of short-circuit power. - Koichi Nose; Takayasu Sakurai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

VTH-hopping scheme for 82% power saving in low-voltage processors. - Koichi Nose; Masayuki Hirabayashi; Hiroshi Kawaguchi 001; Seongsoo Lee; Takayasu Sakurai (CICC, 2001)

Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. - Youngsoo Shin; Hiroshi Kawaguchi 001; Takayasu Sakurai (CICC, 2001)

Coupling-Driven Bus Design for Low-Power Application-Specific Systems. - Youngsoo Shin; Takayasu Sakurai (DAC, 2001)

An LSI for VDD-hopping and MPEG4 system based on the chip. - Hiroshi Kawaguchi 001; Gang Zhang; Seongsoo Lee; Takayasu Sakurai (ISCAS (4), 2001)

Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. - Masayuki Hirabayashi; Koichi Nose; Takayasu Sakurai (ISLPED, 2001)

Variable threshold CMOS (VTCMOS) in series connected circuits. - Takashi Inukai; Toshiro Hiramoto; Takayasu Sakurai (ISLPED, 2001)

Estimation of power distribution in VLSI interconnects. - Youngsoo Shin; Takayasu Sakurai (ISLPED, 2001)

Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. - Kouichi Kanda; Kouichi Nose; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE J. Solid State Circuits, 2001)

Power-conscious Scheduling for Real-time Embedded Systems Design. - Youngsoo Shin; Kiyoung Choi; Takayasu Sakurai (VLSI Design, 2001)

Minimizing power across multiple technology and design levels. - Takayasu Sakurai (ICCAD, 2002)

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. - Kyeong-Sik Min; Young-Hee Kim; Jin-Hong Ahn; Jin-Yong Chung; Takayasu Sakurai (ISCAS (5), 2002)

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. - Koichi Nose; Takayasu Sakurai (ISLPED, 2002)

Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). - Takayasu Sakurai (ISQED, 2002)

Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. - Seongsoo Lee; Seungjun Lee; Takayasu Sakurai (J. Circuits Syst. Comput., 2002)

VTH-hopping scheme to reduce subthreshold leakage for low-power processors. - Koichi Nose; Masayuki Hirabayashi; Hiroshi Kawaguchi 001; Seongsoo Lee; Takayasu Sakurai (IEEE J. Solid State Circuits, 2002)

Power distribution analysis of VLSI interconnects using model orderreduction. - Youngsoo Shin; Takayasu Sakurai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments. - Jin-Hyeok Choi; Takayasu Sakurai (CICC, 2003)

Reshaping EDA for power. - Jan M. Rabaey; Dennis Sylvester; David T. Blaauw; Kerry Bernstein; Jerry Frenkil; Mark Horowitz; Wolfgang Nebel; Takayasu Sakurai; Andrew Yang (DAC, 2003)

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model. - Hyunsik Im; Takashi Inukai; Hiroyuki Gomyo; Toshiro Hiramoto; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Cross talk countermeasures in inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (CICC, 2004)

Observation of one-fifth-of-a-clock wake-up time of power-gated circuit. - Takayuki Miyazaki; Canh Quang Tran; Hiroshi Kawaguchi 001; Takayasu Sakurai (CICC, 2004)

Low power digital circuit design. - Takayasu Sakurai (ESSCIRC, 2004)

Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain. - Jin-Hyeok Choi; Yingxue Xu; Takayasu Sakurai (IEEE J. Solid State Circuits, 2004)

90% write power-saving SRAM using sense-amplifying memory cell. - Kouichi Kanda; Hattori Sadaaki; Takayasu Sakurai (IEEE J. Solid State Circuits, 2004)

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). - Koichi Ishida; Kouichi Kanda; Atit Tamtrakarn; Hiroshi Kawaguchi 001; Takayasu Sakurai (ISCAS (4), 2005)

More than two orders of magnitude leakage current reduction in look-up table for FPGAs. - Canh Quang Tran; Hiroshi Kawaguchi 001; Takayasu Sakurai (ISCAS (5), 2005)

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. - Kyeong-Sik Min; Kouichi Kanda; Hiroshi Kawaguchi 001; Kenichi Inagaki; Fayez Robert Saliba; Hoon-Dae Choi; Hyun-Young Choi; Daejeong Kim; Dong Myong Kim; Takayasu Sakurai (IEICE Trans. Electron., 2005)

Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. - Hiroshi Kawaguchi 001; Takao Someya; Tsuyoshi Sekitani; Takayasu Sakurai (IEEE J. Solid State Circuits, 2005)

Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect. - Noriyuki Miura; Daisuke Mizoguchi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2005)

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. - Keisuke Toyama 003; Satoshi Misaka; Kazuo Aisaka; Toshiyuki Aritsuka; Kunio Uchiyama; Koichiro Ishibashi; Hiroshi Kawaguchi 001; Takayasu Sakurai (Syst. Comput. Jpn., 2005)

μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. - Hiroshi Kawaguchi 001; Youngsoo Shin; Takayasu Sakurai (IEEE Trans. Multim., 2005)

A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. - Koichi Ishida; Atit Tamtrakarn; Takayasu Sakurai (ASP-DAC, 2006)

Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. - Kohei Onizuka; Hiroshi Kawaguchi 001; Makoto Takamiya; Tadahiro Kuroda; Takayasu Sakurai (CICC, 2006)

Compact outside-rail circuit structure by single-cascode two-transistor topology. - Atit Tamtrakarn; Hiroki Ishikuro; Koichi Ishida; Takayasu Sakurai (CICC, 2006)

A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2006)

An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. - Makoto Takamiya; Tsuyoshi Sekitani; Yusaku Kato; Hiroshi Kawaguchi 001; Teruki Someya; Takayasu Sakurai (ISSCC, 2006)

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. - Danardono Dwi Antono; Kenichi Inagaki; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. - Danardono Dwi Antono; Kenichi Inagaki; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEICE Trans. Electron., 2006)

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. - Daisuke Mizoguchi; Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2006)

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. - Canh Quang Tran; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEICE Trans. Electron., 2006)

Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). - Koichi Ishida; Kouichi Kanda; Atit Tamtrakarn; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE J. Solid State Circuits, 2006)

A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2006)

$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. - Kohei Onizuka; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2006)

Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. - Kyeong-Sik Min; Hun-Dae Choi; H.-Y. Choi; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". - Takayasu Sakurai (ASP-DAC, 2007)

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS. - David Levacq; Takuya Minakawa; Makoto Takamiya; Takayasu Sakurai (CICC, 2007)

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. - David Levacq; Muhammad Yazid; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (ESSCIRC, 2007)

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2007)

Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches. - Makoto Takamiya; Tsuyoshi Sekitani; Yoshio Miyamoto; Yoshiaki Noguchi; Hiroshi Kawaguchi 001; Takao Someya; Takayasu Sakurai (ISSCC, 2007)

Meeting with the forthcoming IC design. - Takayasu Sakurai (SBCCI, 2007)

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. - Koichi Ishida; Atit Tamtrakarn; Hiroki Ishikuro; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2007)

Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. - Hiroshi Kawaguchi 001; Danardono Dwi Antono; Takayasu Sakurai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. - Kiichi Niitsu; Noriyuki Miura; Mari Inoue; Yoshihiro Nakagawa; Masamoto Tago; Masayuki Mizuno; Takayasu Sakurai; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's. - Fayez Robert Saliba; Hiroshi Kawaguchi 001; Takayasu Sakurai (IEICE Trans. Electron., 2007)

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link. - Noriyuki Miura; Daisuke Mizoguchi; Mari Inoue; Kiichi Niitsu; Yoshihiro Nakagawa; Masamoto Tago; Muneo Fukaishi; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array. - Noriyuki Miura; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2007)

Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. - Kohei Onizuka; Kenichi Inagaki; Hiroshi Kawaguchi 001; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2007)

An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. - Makoto Takamiya; Tsuyoshi Sekitani; Yusaku Kato; Hiroshi Kawaguchi 001; Takao Someya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2007)

1/5 power reduction by global optimization based on fine-grained body biasing. - Yasumi Nakamura; David Levacq; Limin Xiao; Takuya Minakawa; Taro Niiyama; Makoto Takamiya; Takayasu Sakurai (CICC, 2008)

Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's. - Taro Niiyama; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (CICC, 2008)

Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node. - Sungdae Choi; Katsuyuki Ikeuchi; Hyunkyung Kim; Kenichi Inagaki; Masami Murakata; Nobuyuki Nishiguchi; Makoto Takamiya; Takayasu Sakurai (ESSCIRC, 2008)

Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future. - Takayasu Sakurai (ESSCIRC, 2008)

Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. - Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2008)

Next-generation power-aware design. - Takayasu Sakurai (ISLPED, 2008)

Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. - Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (ISQED, 2008)

A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet. - Lechang Liu; Makoto Takamiya; Tsuyoshi Sekitani; Yoshiaki Noguchi; Shintaro Nakano; Koichiro Zaitsu; Tadahiro Kuroda; Takao Someya; Takayasu Sakurai (ISSCC, 2008)

An 11Gb/s Inductive-Coupling Link with Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2008)

Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time. - David Levacq; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2008)

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping. - Noriyuki Miura; Hiroki Ishikuro; Kiichi Niitsu; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A capacitive coupling interface with high sensitivity for wireless wafer testing. - Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (3DIC, 2009)

Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (3DIC, 2009)

A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. - Lechang Liu; Yoshio Miyamoto; Zhiwei Zhou; Kosuke Sakaida; Jisun Ryu; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (ASP-DAC, 2009)

Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. - Katsuyuki Ikeuchi; Kosuke Sakaida; Koichi Ishida; Takayasu Sakurai; Makoto Takamiya (CICC, 2009)

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISLPED, 2009)

A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. - Koichi Ishida; Naoki Masunaga; Zhiwei Zhou; Tadashi Yasufuku; Tsuyoshi Sekitani; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2009)

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISSCC, 2009)

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. - Yasufumi Sugimori; Yoshinori Kohama; Mitsuko Saito; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (ISSCC, 2009)

A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS. - Lechang Liu; Yoshio Miyamoto; Zhiwei Zhou; Kosuke Sakaida; Jisun Ryu; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2009)

An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise. - Yasumi Nakamura; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2009)

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering. - Makoto Takamiya; Takayasu Sakurai (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A High-Speed Inductive-Coupling Link With Burst Transmission. - Noriyuki Miura; Yoshinori Kohama; Yasufumi Sugimori; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2009)

A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems. - Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. - Lechang Liu; Makoto Takamiya; Tsuyoshi Sekitani; Yoshiaki Noguchi; Shintaro Nakano; Koichiro Zaitsu; Tadahiro Kuroda; Takao Someya; Takayasu Sakurai (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. - Koichi Ishida; Koichi Takemura; Kazuhiro Baba; Makoto Takamiya; Takayasu Sakurai (3DIC, 2010)

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems. - Gil-Su Kim; Katsuyuki Ikeuchi; Mutsuo Daito; Makoto Takamiya; Takayasu Sakurai (3DIC, 2010)

0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuaki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (CICC, 2010)

EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision. - Naoki Masunaga; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (CICC, 2010)

0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. - Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Xin Zhang 025; Po-Hung Chen; Kazunori Watanabe; Makoto Takamiya; Takayasu Sakurai (CICC, 2010)

Misleading energy and performance claims in sub/near threshold digital systems. - Yu Pu; Xin Zhang 025; Jim Huang; Atsushi Muramatsu; Masahiro Nomura; Koji Hirairi; Hidehiro Takata; Taro Sakurabayashi; Shinji Miyano; Makoto Takamiya; Takayasu Sakurai (ICCAD, 2010)

Design of large area electronics with organic transistors. - Makoto Takamiya; Koichi Ishida; Tsuyoshi Sekitani; Takao Someya; Takayasu Sakurai (ICCAD, 2010)

The semiconductor industry in 2025. - Azeez Bhavnagarwala; Shekhar Borkar; Takayasu Sakurai; Siva G. Narendra (ISSCC, 2010)

User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. - Koichi Ishida; Naoki Masunaga; Ryo Takahashi; Tsuyoshi Sekitani; Shigeki Shino; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2010)

Silicon 3D-integration technology and systems. - Pascal Urard; Ken Takeuchi; Kerry Bernstein; Hideto Hidaka; Michael Phan; Joo-Sun Choi; Bob Payne; Vladimir Stojanovic; Kees van Berkel 001; Takayasu Sakurai (ISSCC, 2010)

A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS. - Lechang Liu; Zhiwei Zhou; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2010)

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEICE Trans. Electron., 2010)

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. - Tadashi Yasufuku; Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2010)

Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. - Koichi Ishida; Naoki Masunaga; Zhiwei Zhou; Tadashi Yasufuku; Tsuyoshi Sekitani; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2010)

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. - Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2010)

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. - Youngsoo Shin; Jun Seomun; Kyu-Myung Choi; Takayasu Sakurai (ACM Trans. Design Autom. Electr. Syst., 2010)

Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies. - Katsuyuki Ikeuchi; Makoto Takamiya; Takayasu Sakurai (3DIC, 2011)

An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. - Xin Zhang 025; Koichi Ishida; Makoto Takamiya; Takayasu Sakurai (ASP-DAC, 2011)

A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (A-SSCC, 2011)

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. - Shinichi Moriwaki; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Shinji Miyano (CICC, 2011)

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. - Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (DAC, 2011)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. - Atsushi Muramatsu; Tadashi Yasufuku; Masahiro Nomura; Makoto Takamiya; Hirofumi Shinohara; Takayasu Sakurai (ESSCIRC, 2011)

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISLPED, 2011)

Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection. - Kentaro Honda; Katsuyuki Ikeuchi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2011)

Designing ultra-low voltage logic. - Takayasu Sakurai (ISLPED, 2011)

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. - Tadashi Yasufuku; Satoshi Iida; Hiroshi Fuketa; Koji Hirairi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2011)

A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. - Po-Hung Chen; Koichi Ishida; Katsuyuki Ikeuchi; Xin Zhang 025; Kentaro Honda; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (ISSCC, 2011)

100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Tsuyoshi Sekitani; Hiroyoshi Nakajima; Hiroki Maeda; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2011)

Beyond the horizon: The next 10x reduction in power - Challenges and solutions. - Jan M. Rabaey; Hugo De Man; Mark Horowitz; Takayasu Sakurai; Jack Sun; Dan Dobberpuhl; Kiyoo Itoh 001; Philippe Magarshack; Asad A. Abidi; Hermann Eul (ISSCC, 2011)

0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling. - Katsuyuki Ikeuchi; Hideki Kusamitsu; Mutsuo Daito; Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver. - Lechang Liu; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2011)

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. - Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Xin Zhang 025; Po-Hung Chen; Kazunori Watanabe; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout. - Tadashi Yasufuku; Yasumi Nakamura; Piao Zhe; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. - Xin Zhang 025; Yu Pu; Koichi Ishida; Yoshikatsu Ryu; Yasuyuki Okuma; Po-Hung Chen; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2011)

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. - Mutsuo Daito; Yoshiro Nakata; Satoshi Sasaki; Hiroyuki Gomyo; Hideki Kusamitsu; Yoshio Komoto; Kunihiko Iizuka; Katsuyuki Ikeuchi; Gil-Su Kim; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2011)

User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. - Koichi Ishida; Naoki Masunaga; Ryo Takahashi; Tsuyoshi Sekitani; Shigeki Shino; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2011)

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver. - Lechang Liu; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2011)

Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. - Yu Pu; Xin Zhang 025; Katsuyuki Ikeuchi; Atsushi Muramatsu; Atsushi Kawasumi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. - Po-Hung Chen; Koichi Ishida; Xin Zhang 025; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (ASP-DAC, 2012)

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (CICC, 2012)

2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm. - Shunta Iguchi; Akira Saito; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (ESSCIRC, 2012)

0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS. - Akira Saito; Yun Fei Zheng; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (ISLPED, 2012)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. - Tadashi Yasufuku; Koji Hirairi; Yu Pu; Yun Fei Zheng; Ryo Takahashi; Masato Sasaki; Hiroshi Fuketa; Atsushi Muramatsu; Masahiro Nomura; Hirofumi Shinohara; Makoto Takamiya; Takayasu Sakurai (ISQED, 2012)

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. - Koji Hirairi; Yasuyuki Okuma; Hiroshi Fuketa; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISSCC, 2012)

Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Yasuhiro Shinozuka; Hiroshi Fuketa; Tomoyuki Yokota; Ute Zschieschang; Hagen Klauk; Gregory Tortissier; Tsuyoshi Sekitani; Makoto Takamiya; Hiroshi Toshiyoshi; et al. (ISSCC, 2012)

Ambient electronics and ultra-low power LSI design. - Takayasu Sakurai (VLSI-DAT, 2012)

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. - Shinichi Moriwaki; Yasuhiro Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Shinji Miyano; Takayasu Sakurai; Hirofumi Shinohara (VLSIC, 2012)

An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS. - Akira Saito; Kentaro Honda; Yun Fei Zheng; Shunta Iguchi; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (VLSIC, 2012)

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW. - Xin Zhang 025; Po-Hung Chen; Yoshikatsu Ryu; Koichi Ishida; Yasuyuki Okuma; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (VLSIC, 2012)

A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network. - Lechang Liu; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2012)

EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution. - Naoki Masunaga; Koichi Ishida; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2012)

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. - Po-Hung Chen; Koichi Ishida; Katsuyuki Ikeuchi; Xin Zhang 025; Kentaro Honda; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2012)

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. - Po-Hung Chen; Xin Zhang 025; Koichi Ishida; Yasuyuki Okuma; Yoshikatsu Ryu; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2012)

A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Tsuyoshi Sekitani; Hiroyoshi Nakajima; Hiroki Maeda; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2012)

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. - Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. - Xin Zhang 025; Yu Pu; Koichi Ishida; Yoshikatsu Ryu; Yasuyuki Okuma; Po-Hung Chen; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. - Xin Zhang 025; Koichi Ishida; Hiroshi Fuketa; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Variation-aware subthreshold logic circuit design. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ASICON, 2013)

315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS. - Shunta Iguchi; Akira Saito; Kentaro Honda; Yun Fei Zheng; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (ASP-DAC, 2013)

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. - Xin Zhang 025; Po-Hung Chen; Yoshikatsu Ryu; Koichi Ishida; Yasuyuki Okuma; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (ASP-DAC, 2013)

Electrical artificial skin using ultraflexible organic transistor. - Tsuyoshi Sekitani; Tomoyuki Yokota; Makoto Takamiya; Takayasu Sakurai; Takao Someya (DAC, 2013)

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme. - Yasuhiro Shinozuka; Hiroshi Fuketa; Koichi Ishida; Futoshi Furuta; Kenichi Osada; Kenichi Takeda; Makoto Takamiya; Takayasu Sakurai (ISQED, 2013)

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. - Hiroshi Fuketa; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISSCC, 2013)

1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. - Hiroshi Fuketa; Kazuaki Yoshioka; Yasuhiro Shinozuka; Koichi Ishida; Tomoyuki Yokota; Naoji Matsuhisa; Yusuke Inoue 002; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2013)

Large-area and flexible sensors with organic transistors. - Hiroshi Fuketa; Koichi Ishida; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IWASI, 2013)

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. - Hiroshi Fuketa; Ryo Takahashi; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE J. Solid State Circuits, 2013)

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. - Koichi Ishida; Tsung-Ching Huang; Kentaro Honda; Yasuhiro Shinozuka; Hiroshi Fuketa; Tomoyuki Yokota; Ute Zschieschang; Hagen Klauk; Gregory Tortissier; Tsuyoshi Sekitani; Hiroshi Toshiyoshi; Makoto Takamiya; et al. (IEEE J. Solid State Circuits, 2013)

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. - Shinji Miyano; Shinichi Moriwaki; Yasue Yamamoto; Atsushi Kawasumi; Toshikazu Suzuki; Takayasu Sakurai; Hirofumi Shinohara (IEEE J. Solid State Circuits, 2013)

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2013)

An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting. - Hiroshi Fuketa; Youichi Momiyama; Atsushi Okamoto; Tsuyoshi Sakata; Makoto Takamiya; Takayasu Sakurai (ESSCIRC, 2014)

30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance. - Hiroshi Fuketa; Kazuaki Yoshioka; Tomoyuki Yokota; Wakako Yukita; Mari Koizumi; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2014)

Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications. - Makoto Takamiya; Hiroshi Fuketa; Koichi Ishida; Tomoyuki Yokota; Tsuyoshi Sekitani; Takao Someya; Takayasu Sakurai (MWSCAS, 2014)

92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. - Shunta Iguchi; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (VLSIC, 2014)

Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. - Hiroshi Fuketa; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2014)

A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS. - Xin Zhang 025; Po-Hung Chen; Yasuyuki Okuma; Koichi Ishida; Yoshikatsu Ryu; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2014)

1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control. - Hiroshi Fuketa; Kazuaki Yoshioka; Yasuhiro Shinozuka; Koichi Ishida; Tomoyuki Yokota; Naoji Matsuhisa; Yusuke Inoue 002; Masaki Sekino; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE Trans. Biomed. Circuits Syst., 2014)

Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter. - Shunta Iguchi; Akira Saito; Kazunori Watanabe; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit. - Dan Luo; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Makoto Takamiya; Takayasu Sakurai (ECCTD, 2015)

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (ESSCIRC, 2015)

Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications. - Yoshitaka Yamauchi; Yuki Yanagihara; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (ICICDT, 2015)

16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits. - Hiroshi Fuketa; Masamune Hamamatsu; Tomoyuki Yokota; Wakako Yukita; Teruki Someya; Tsuyoshi Sekitani; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2015)

Wireless Power Transfer With Zero-Phase-Difference Capacitance Control. - Shunta Iguchi; Pyungwoo Yeon; Hiroshi Fuketa; Koichi Ishida; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

56-Level programmable voltage detector in steps of 50mV for battery management. - Teruki Someya; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (A-SSCC, 2016)

5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage. - Shunta Iguchi; Takayasu Sakurai; Makoto Takamiya (ISSCC, 2016)

Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster. - Shunta Iguchi; Hiroshi Fuketa; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2016)

Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control. - Chung-Shiang Wu; Makoto Takamiya; Takayasu Sakurai (CICC, 2017)

Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply. - Yoshitaka Yamauchi; Toru Sai; Takayasu Sakurai; Makoto Takamiya (ISCAS, 2017)

Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors. - Islam A. K. M. Mahfuzul; Masamune Hamamatsu; Tomoyuki Yokota; Sunghoon Lee; Wakako Yukita; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier. - Teruki Someya; Hiroshi Fuketa; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (IEICE Trans. Electron., 2017)

A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture. - Shunta Iguchi; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2017)

A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage. - Teruki Someya; Islam A. K. M. Mahfuzul; Takayasu Sakurai; Makoto Takamiya (CICC, 2018)

2/3 and 1/2 Reconfigurable Switched Capacitor DC-DC Converter With 92.9% Efficiency at 62 mW/mm2 Using Driver Amplitude Doubler. - Toru Sai; Yoshitaka Yamauchi; Hajime Kando; Tatsuya Funaki; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes. - Chung-Shiang Wu; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune Receiver Scheme for Power Electronics. - Tsukasa Kagaya; Koutaro Miyazaki; Makoto Takamiya; Takayasu Sakurai (ICICDT, 2019)

CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring. - Koutaro Miyazaki; Yang Lo; A. K. M. Mahfuzul Islam; Katsuhiro Hata; Makoto Takamiya; Takayasu Sakurai (ICICDT, 2019)

Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit. - Yu-Shan Cheng; Daiki Yamaguchi; Tomoyuki Mannen; Keiji Wada; Toru Sai; Koutaro Miyazaki; Makoto Takamiya; Takayasu Sakurai (IECON, 2019)

Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. - Hao Qiu; Takayasu Sakurai; Makoto Takamiya (ISCAS, 2019)

An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage. - Teruki Someya; A. K. M. Mahfuzul Islam; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2019)

A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management. - Teruki Someya; Kenichi Matsunaga; Hiroki Morimura; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Analysis and Mitigation of Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System. - Hao Qiu; Yuntao Jiang; Yi Shi; Takayasu Sakurai; Makoto Takamiya (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC. - Hao Qiu; Takayasu Sakurai; Makoto Takamiya (IEEE J. Solid State Circuits, 2022)

High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions. - Yu-Shan Cheng; Daiki Yamaguchi; Tomoyuki Mannen; Keiji Wada; Toru Sai; Koutaro Miyazaki; Makoto Takamiya; Takayasu Sakurai (IEEE Trans. Ind. Electron., 2022)

Estimating of IGBT Bond Wire Lift-Off Trend Using Convolutional Neural Network (CNN). - Thatree Mamee; Zaiqi Lou; Katsuhiro Hata; Makoto Takamiya; Takayasu Sakurai; Shinichi Nishizawa; Wataru Saito (IEEE Access, 2024)