A 110-MHz/1-Mb synchronous TagRAM. - Yasuo Unekawa; Tsuguo Kobayashi; Tsukasa Shirotori; Yukihiro Fujimoto; Takayoshi Shimazawa; Kazutaka Nogami; Takehiko Nakao; Kazukiro Sawada; Masataka Matsui; Takayasu Sakurai; Man Kit Tang; William A. Huffman (IEEE J. Solid State Circuits, 1994)

300MHz design methodology of VU for emotion synthesis. - Takayuki Kamei; Hideaki Takeda 002; Yukio Ootaguro; Takayoshi Shimazawa; Kazuhiko Tachibana; Shin'ichi Kawakami; Seiji Norimatsu; Fujio Ishihara; Toshinori Sato; Hiroaki Murakami; Nobuhiro Ide; Yukio Endo; et al. (ASP-DAC, 2000)

Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. - Norman Kojima; Yukiko Parameswar; Christian Klingner; Yukio Ohtaguro; Masataka Matsui; Shigeaki Iwasa; Tatsuo Teruyama; Takayoshi Shimazawa; Hideki Takeda; Kouji Hashizume; Haruyuki Tago; Masaaki Yamada (ASP-DAC, 2000)

A single-chip MPEG-2 codec based on customizable media microprocessor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (CICC, 2002)

A single-chip MPEG-2 codec based on customizable media embedded processor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (IEEE J. Solid State Circuits, 2003)

A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. - Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Chen Kong Teh; Takayoshi Shimazawa; Naoyuki Kawabe; Takeshi Kitahara; Yu Kikuchi; Tsuyoshi Nishikawa; Makoto Takahashi; Yukihito Oowaki (CICC, 2005)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

An automated runtime power-gating scheme. - Mototsugu Hamada; Takeshi Kitahara; Naoyuki Kawabe; Hironori Sato; Tsuyoshi Nishikawa; Takayoshi Shimazawa; Takahiro Yamashita; Hiroyuki Hara; Yukihito Oowaki (ICCD, 2007)

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Takayoshi Shimazawa; Yasuo Ohara; Takashi Miyamori; et al. (ISSCC, 2010)

Development of low power and high performance application processor (T6G) for multimedia mobile applications. - Yoshiyuki Kitasho; Yu Kikuchi; Takayoshi Shimazawa; Yasuo Ohara; Masafumi Takahashi; Yoshio Masubuchi; Yukihito Oowaki (ASP-DAC, 2011)

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM. - Yu Kikuchi; Makoto Takahashi; Tomohisa Maeda; Masatoshi Fukuda; Yasuhiro Koshio; Hiroyuki Hara; Hideho Arakida; Hideaki Yamamoto; Yousuke Hagiwara; Tetsuya Fujita; Manabu Watanabe; Hirokazu Ezawa; et al. (IEEE J. Solid State Circuits, 2011)