Worst-case delay analysis considering the variability of transistors and interconnects. - Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (ISPD, 2007)

Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. - Haruhiko Terada; Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Statistical Gate Delay Model for Multiple Input Switching. - Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)