Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. - Hans Jürgen Mattausch; Takayuki Gyohten; Yoshihiro Soda; Tetsushi Koide (IEEE J. Solid State Circuits, 2002)

A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. - Tetsushi Koide; Hans Jürgen Mattausch; Yuji Yano; Takayuki Gyohten; Yoshihiro Soda (ASP-DAC, 2003)

A capacitorless twin-transistor random access memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (CICC, 2005)

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. - Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)