Using Symbolic Model Checking to Detect Service Interactions in Telecommunication Services. - Takayuki Hamada; Tatsuhiro Tsuchiya; Masahide Nakamura; Tohru Kikuno (ICOIN (1), 2002)

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS. - Hisakatsu Yamaguchi; Hirotaka Tamura; Yoshiyasu Doi; Yasumoto Tomita; Takayuki Hamada; Masaya Kibune; Shuhei Ohmoto; Keita Tateishi; Oleksiy Tyshchenko; Ali Sheikholeslami; Tomokazu Higuchi; Junji Ogawa; et al. (ISSCC, 2010)

Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC. - Yanfei Chen; Xiaolei Zhu 002; Hirotaka Tamura; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Masato Yoshioka; Kiyoshi Ishikawa; Takeshi Takayama; Junji Ogawa; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Electron., 2010)

A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology. - Xiaolei Zhu 002; Yanfei Chen; Masaya Kibune; Yasumoto Tomita; Takayuki Hamada; Hirotaka Tamura; Sanroku Tsukamoto; Tadahiro Kuroda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)

Inferring win-lose product network from user behavior. - Shuhei Iitsuka; Kazuya Kawakami; Seigen Hagiwara; Takayoshi Kawakami; Takayuki Hamada; Yutaka Matsuo (WI, 2017)