An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. - Mariko Kaku; Hitoshi Iwai; Takeshi Nagai; Masaharu Wada; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Takayuki Iwai; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano; et al. (ISSCC, 2008)

A 56 Gb/s PAM4 receiver with low-overhead threshold and edge-based DFE FIR and IIR-tap adaptation in 65nm CMOS. - Ashkan Roshan-Zamir; Takayuki Iwai; Yang-Hang Fan; Ankur Kumar; Hae-Woong Yang; Lee Sledjeski; John Hamilton; Soumya Chandramouli; Arlo Aude; Samuel Palermo (CICC, 2018)

A 32 Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver with Adaptive Echo Cancellation in 28nm CMOS. - Yang-Hang Fan; Ankur Kumar; Takayuki Iwai; Ashkan Roshan-Zamir; Shengchang Cai; Bo Sun; Samuel Palermo (CICC, 2019)

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS. - Ashkan Roshan-Zamir; Takayuki Iwai; Yang-Hang Fan; Ankur Kumar; Hae-Woong Yang; Lee Sledjeski; John Hamilton; Soumya Chandramouli; Arlo Aude; Samuel Palermo (IEEE J. Solid State Circuits, 2019)

A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques. - Yang-Hang Fan; Ankur Kumar; Takayuki Iwai; Ashkan Roshan-Zamir; Shengchang Cai; Bo Sun; Samuel Palermo (IEEE J. Solid State Circuits, 2020)