A 1-Mbit BiCMOS DRAM using temperature-compensation circuit techniques. - Goro Kitsukawa; Kiyoo Itoh 001; Ryoichi Hori; Yoshiki Kawajiri; Takao Watanabe; Takayuki Kawahara; Tetsuro Matsumoto; Yutaka Kobayashi (IEEE J. Solid State Circuits, 1989)

Comparison of CMOS and BiCMOS 1-Mbit DRAM performance. - Takao Watanabe; Goro Kitsukawa; Yoshiki Kawajiri; Kiyoo Itoh 001; Ryoichi Hori; Yoshiaki Ouchi; Takayuki Kawahara; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

Substrate current reduction techniques for BiCMOS DRAM. - Takayuki Kawahara; Goro Kitsukawa; Hisayuki Higuchi; Yoshiki Kawajiri; Takao Watanabe; Kiyoo Itoh 001; Ryoichi Hori; Yutaka Kobayashi; Tetsuro Matsumoto (IEEE J. Solid State Circuits, 1989)

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Yoshinobu Nakagome; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1991)

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-Mb DRAM's. - Takayuki Kawahara; Yoshiki Kawajiri; Goro Kitsukawa; Kazuhiko Sagara; Yoshifumi Kawamoto; Takesada Akiba; Shisei Kato; Yasushi Kawase; Kiyoo Itoh 001 (IEEE J. Solid State Circuits, 1992)

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays. - Takayuki Kawahara; Takeshi Sakata; Kiyoo Itoh 001; Yoshiki Kawajiri; Takesada Akiba; Goro Kitsukawa; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs). - Takayuki Kawahara; Masashi Horiguchi; Yoshiki Kawajiri; Goro Kitsukawa; Tokuo Kure; Masakazu Aoki (IEEE J. Solid State Circuits, 1993)

256-Mb DRAM circuit technologies for file applications. - Goro Kitsukawa; Masashi Horiguchi; Yoshiki Kawajiri; Takayuki Kawahara; Takesada Akiba; Yasushi Kawase; Toshikazu Tachibana; Takeshi Sakai; Masakazu Aoki; Syoji Shukuri; Kazuhiko Sagara; Ryo Nagai; et al. (IEEE J. Solid State Circuits, 1993)

High reliability electron-ejection method for high density flash memories. - Takayuki Kawahara; Naoki Miyamoto; Syun-ichi Saeki; Yusuke Jyouno; Masataka Kato; Katsutaka Kimura (IEEE J. Solid State Circuits, 1995)

Bit-line clamped sensing multiplex and accurate high voltage generator for quarter-micron flash memories. - Takayuki Kawahara; Takashi Kobayashi 002; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; T. Adachi; Masataka Kato; Akihiko Sato; J. Yugami; Hitoshi Kume; Katsutaka Kimura (IEEE J. Solid State Circuits, 1996)

20-Mb/s erase/record flash memory by asymmetrical operation. - Takayuki Kawahara; Yusuke Jyouno; Syun-ichi Saeki; Naoki Miyamoto; Katsutaka Kimura (IEEE J. Solid State Circuits, 1998)

Internal voltage generator for low voltage, quarter-micrometer flash memories. - Takayuki Kawahara; Syun-ichi Saeki; Yusuke Jyouno; Naoki Miyamoto; Takashi Kobayashi 002; Katsutaka Kimura (IEEE J. Solid State Circuits, 1998)

Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. - Masayuki Miyazaki; Hidetoshi Tanaka; Goichi Ono; Tomohiro Nagano; Norio Ohkubo; Takayuki Kawahara; Kazuo Yano (ISLPED, 2003)

Review and future prospects of low-voltage RAM circuits. - Yoshinobu Nakagome; Masashi Horiguchi; Takayuki Kawahara; Kiyoo Itoh 001 (IBM J. Res. Dev., 2003)

Analysis of SRAM neutron-induced errors based on the consideration of both charge-collection and parasitic-bipolar failure modes. - Kenichi Osada; Naoki Kitai; Shiro Kamohara; Takayuki Kawahara (CICC, 2004)

Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]. - Goichi Ono; Masayuki Miyazaki; Hidetoshi Tanaka; Nono Ohkubo; Takayuki Kawahara (ESSCIRC, 2004)

Low-Voltage Embedded RAMs - Current Status and Future Trends. - Kiyoo Itoh 001; Kenichi Osada; Takayuki Kawahara (PATMOS, 2004)

SRAM immunity to cosmic-ray-induced multierrors based on analysis of an induced parasitic bipolar effect. - Kenichi Osada; Ken Yamaguchi; Yoshikazu Saitoh; Takayuki Kawahara (IEEE J. Solid State Circuits, 2004)

Phase change RAM operated with 1.5-V CMOS as low cost embedded memory. - Kenichi Osada; Takayuki Kawahara; Riichiro Takemura; Naoki Kitai; Norikatsu Takaura; Nozomu Matsuzaki; Kenzo Kurotsuchi; Hiroshi Moriya; Masahiro Moniwa (CICC, 2005)

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Tomonori Sekiguchi; Takayuki Kawahara (ICC, 2005)

Optimum threshold-voltage tuning for low-power, high-performance microprocessor. - Masayuki Miyazaki; Goichi Ono; Takayuki Kawahara (ISCAS (1), 2005)

An LSI system with locked in temperature insensitive state achieved by using body bias technique. - Goichi Ono; Masayuki Miyazaki; Kazuki Watanabe 008; Takayuki Kawahara (ISCAS (1), 2005)

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router. - Satoru Hanzawa; Takeshi Sakata; Kazuhiko Kajigaya; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories. - Hideaki Kurata; Shunichi Saeki; Takashi Kobayashi 002; Yoshitaka Sasago; Tsuyoshi Arigane; Kazuo Otsuga; Takayuki Kawahara (IEEE J. Solid State Circuits, 2005)

Ultra-low voltage nano-scale embedded RAMs. - Kiyoo Itoh 001; Masashi Horiguchi; Takayuki Kawahara (ISCAS, 2006)

Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. - Satoru Akiyama; Tomonori Sekiguchi; Kazuhiko Kajigaya; Satoru Hanzawa; Riichiro Takemura; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique. - Masanao Yamaoka; Noriaki Maeda; Yoshihiro Shinozaki; Yasuhisa Shimazaki; Koji Nii; Shigeru Shimada; Kazumasa Yanagisawa; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors. - Masanao Yamaoka; Ryuta Tsuchiya; Takayuki Kawahara (IEEE J. Solid State Circuits, 2006)

Operating-margin-improved SRAM with column-at-a-time body-bias control technique. - Masanao Yamaoka; Takayuki Kawahara (ESSCIRC, 2007)

Low-voltage limitations of deep-sub-100-nm CMOS LSIs: view of memory designers. - Kiyoo Itoh 001; Masanao Yamaoka; Takayuki Kawahara (ACM Great Lakes Symposium on VLSI, 2007)

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. - Takayuki Kawahara; Riichiro Takemura; Hiromasa Takahashi; Hideo Ohno (ICECS, 2007)

A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. - Satoru Hanzawa; Naoki Kitai; Kenichi Osada; Akira Kotabe; Yuichi Matsui; Nozomu Matsuzaki; Norikatsu Takaura; Masahiro Moniwa; Takayuki Kawahara (ISSCC, 2007)

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (ISSCC, 2007)

Low-Voltage Embedded RAMs in Nanometer Era. - Takayuki Kawahara (IEICE Trans. Electron., 2007)

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. - Riichiro Takemura; Kiyoo Itoh 001; Tomonori Sekiguchi; Satoru Akiyama; Satoru Hanzawa; Kazuhiko Kajigaya; Takayuki Kawahara (IEICE Trans. Electron., 2007)

A cell-activation-time controlled SRAM for low-voltage operation in DVFS SoCs using dynamic stability analysis. - Masanao Yamaoka; Kenichi Osada; Takayuki Kawahara (ESSCIRC, 2008)

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (IEEE J. Solid State Circuits, 2008)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Scalable Spin-Transfer Torque RAM Technology for Normally-Off Computing. - Takayuki Kawahara (IEEE Des. Test Comput., 2011)

Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. - Yoshimitsu Yanagawa; Kazuo Ono; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (ISCAS, 2012)

Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. - Kazuo Ono; Yoshimitsu Yanagawa; Akira Kotabe; Riichiro Takemura; Tatsuo Nakagawa; Tomio Iwasaki; Takayuki Kawahara (IEICE Trans. Electron., 2012)

Spin-transfer torque RAM technology: Review and prospect. - Takayuki Kawahara; Kenchi Ito; Riichiro Takemura; Hideo Ohno (Microelectron. Reliab., 2012)

On-chip base sequencing using a two-stage reaction-control scheme: 3.6-times-faster and 1/100-reduced-data-volume ISFET-based DNA sequencer. - Yoshimitsu Yanagawa; Naoshi Itabashi; Sonoko Migitaka; Takahide Yokoi; Makiko Yoshida; Takayuki Kawahara (BioCAS, 2013)

What is a good way to expand a silicon value to a solution value? - Tzi-Dar Chiueh; Toru Shimizu; Gregory Chen; Chen-Yi Lee; Charles Hsu; Tihao Chiang; Zhihua Wang 001; Junghwan Choi; Jongwoo Lee; Yasumoto Tomita; Takayuki Kawahara (A-SSCC, 2014)

Equalization for the FDM System Using Mach-Zehnder Filters. - Yuki Fukushima; Isamu Wakabayashi; Takayuki Kawahara (AINA Workshops, 2015)

An eight-channel FDM system using Mach-Zehnder filters with cosine roll-off band-limiting characteristics. - Isamu Wakabayashi; Yuki Fukushima; Takayuki Kawahara (APSITT, 2015)

STT-RAM read stability in DRAM operating region. - H. Kazama; Takayuki Kawahara (NVMTS, 2015)

Novel Ising model using dimension-control for high-speed solver for Ising machines. - Kenta Someya; Ryoto Ono; Takayuki Kawahara (NEWCAS, 2016)

Timber Health Monitoring using piezoelectric sensor and machine learning. - Ryo Oiwa; Takumi Ito; Takayuki Kawahara (CIVEMSA, 2017)

Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. - Yasushi Fukuda; Zule Xu; Takayuki Kawahara (IEICE Trans. Electron., 2017)

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. - Zule Xu; Takayuki Kawahara (IEICE Trans. Electron., 2017)

Wooden Framed House Structural Health Monitoring by System Identification and Damage Detection under Dynamic Motion with Artificial Intelligence Sensor using a Model of House including Braces. - Ryota Tanida; Ryo Oiwa; Takumi Ito; Takayuki Kawahara (CIVEMSA, 2018)

Live Demonstration of IoT and AI System for Recognition of States of Buildings subjected to Seismic Vibration Motion. - Takumi Ito; Changhoon Choi; Takahiro Yamamoto; Takashi Nakajima; Takayuki Kawahara; Yoichiro Hashizume; Mikio Hasegawa (ISCAS, 2018)

Effectiveness of Synchronization and Cooperative Behavior of Multiple Robots based on Swarm AI. - Tatsuya Hiejima; Shun Kawashima; Mengnan Ke; Takayuki Kawahara (APCCAS, 2019)

Machine Learning Classification Methods using Data of 3-axis Acceleration Sensors equipped with Wireless Communication Means for Locating Wooden House Structural Damage. - Ryota Tanida; Jing Ma; Takashi Nakajima; Mikio Hasegawa; Takahiro Yamamoto; Takumi Ito; Takayuki Kawahara; Atsushi Yamamoto; Noriaki Takahashi; Natsuhiko Sakiyama; Sakuya Kishi; Takayuki Kishimoto; et al. (APCCAS, 2019)

High-speed Sparse Ising Model on FPGA. - Akira Minamisawa; Ryoma Iimura; Takayuki Kawahara (MWSCAS, 2019)

Damage-Position Identification of Wooden-House Models for Structural Health Monitoring Using Machine Learning. - Kohei Koike; Kenta Suzuki; Mengnan Ke; Kenjiro Mori; Takumi Ito; Takayuki Kawahara (APCCAS, 2020)

Improvement of Generalization Performance for Timber Health Monitoring using Machine Learning. - Kenta Suzuki; Takumi Ito; Kohei Koike; Takayuki Kawahara; Mengnan Ke; Kenjiro Mori (APCCAS, 2020)

Implementation of Multi Spin-Thread Architecture to Fully-Connected Annealing Processing AI Chips. - Ryoma Iimura; Satoshi Kitamura; Takayuki Kawahara (MWSCAS, 2020)

A novel Ising model processing achieving all interactions only by adjacent spins for a high-speed solver for versatile Ising machines. - Ryoto Ono; Kenta Someya; Takayuki Kawahara (Microprocess. Microsystems, 2020)

FPGA Implementation of Support Vector Machine Using Ising Model for AI on Things. - Yudai Taguchi; Ryoma Iimura; Takayuki Kawahara (CIVEMSA, 2021)

Annealing Processing Architecture of 28-nm CMOS Chip for Ising Model With 512 Fully Connected Spins. - Ryoma Iimura; Satoshi Kitamura; Takayuki Kawahara (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Bi-directional read method to reduce SOT-specific read disturbance for highly reliable SOT-MRAM. - Akihiro Yamada; Yuwa Kishi; Takayuki Kawahara (IMW, 2022)

Scalable fully coupled annealing processing system and multi-chip FPGA implementation. - Kaoru Yamamoto; Takayuki Kawahara (Microprocess. Microsystems, 2022)

BNN Training Algorithm with Ternary Gradients and BNN based on MRAM Array. - Yuya Fujiwara; Takayuki Kawahara (TENCON, 2023)

Experimental Investigation of the Generalization Performance of Neural Network in Defect Localization System for Steel Pipe Health Monitoring. - Yuya Hayakawa; Yuga Aoki; Kenjiro Mori; Takumi Ito; Takayuki Kawahara (TENCON, 2023)

Proposal and Validation of Annealing-processor-calculation Method Using Error-diffusion Rounded Interaction Matrix. - Dong Cui; Takayuki Kawahara (APCCAS, 2024)

Efficient Implementation of Parallel Annealing Method with Heisenberg Model. - Kazuma Kanai; Takayuki Kawahara (APCCAS, 2024)

Method for Measuring Silicon Quantum Dots with TMR Sensor. - Seiji Komatsu; Takayuki Kawahara (APCCAS, 2024)

Proposal and Validation of a Dual Scalable Annealing Processing System That Simultaneously Scales Capacity and Precision. - Dong Cui; Taichi Megumi; Akari Endo; Takayuki Kawahara (ICM, 2024)

TGBNN: Training Algorithm of Binarized Neural Network With Ternary Gradients for MRAM-Based Computing-in-Memory Architecture. - Yuya Fujiwara; Takayuki Kawahara (IEEE Access, 2024)

Implementation and Evaluation of Two Independent Ising Machines on Same FPGA Board by Reducing Number of Interactions Inside Ising Machine. - Shinjiro Kitahara; Taichi Megumi; Akari Endo; Takayuki Kawahara (IEEE Access, 2024)

Scalable Fully-Coupled Annealing Processing System Implementing 4096 Spins Using 22nm CMOS LSI. - Taichi Megumi; Akari Endo; Takayuki Kawahara (IEEE Access, 2024)

Dual Scalable Annealing Processing System That Scales Number of Spins and Interaction Bit Width Simultaneously. - Dong Cui; Taichi Megumi; Akari Endo; Takayuki Kawahara (IEEE Access, 2025)