Microprocessor architecture utilizing redundant-binary operation. - Takahiro Irita; Takayuki Ogura; Minoru Fujishima; Koichiro Hoh (Syst. Comput. Jpn., 1999)

0.18- μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation. - Akira Tanabe; Masato Umetani; Ikuo Fujiwara; Takayuki Ogura; Kotaro Kataoka; Masao Okihara; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka (IEEE J. Solid State Circuits, 2001)