Development of ultra-thinning technology for logic and memory heterogeneous stack applications. - Nobuhide Maeda; Young-Suk Kim; Y. Hikosaka; T. Eshita; Hideki Kitada; K. Fujimoto; Yoriko Mizushima; K. Suzuki; Tadao Nakamura; Akihito Kawai; Kazuhisa Arai; Takayuki Ohba (3DIC, 2011)

Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects. - Tomoji Nakamura; Hideki Kitada; Yoriko Mizushima; Nobuhide Maeda; Koji Fujimoto; Takayuki Ohba (3DIC, 2011)

Characterization of local strain around trough silicon via interconnects in wafer-on-wafer structures. - Osamu Nakatsuka; Hideki Kitada; Young-Suk Kim; Yoriko Mizushima; Tomoji Nakamura; Takayuki Ohba; Shigeaki Zaima (3DIC, 2011)

Influence of wafer thinning process on backside damage in 3D integration. - Tadao Nakamura; Yoriko Mizushima; Hideki Kitada; Young-Suk Kim; Nobuhide Maeda; Shoichi Kodama; Ryuichi Sugie; Hiroshi Hashimoto; Akihito Kawai; Kazuhisa Arai; Akira Uedono; Takayuki Ohba (3DIC, 2013)

Impact of Thermomechanical Stresses on Ultra-thin Si Stacked Structure. - Yoriko Mizushima; Young-Suk Kim; Tomoji Nakamura; Shoichi Kodama; Nobuhide Maeda; Koji Fujimoto; Takayuki Ohba (3DIC, 2014)

Characterization of stress distribution in ultra-thinned DRAM wafer. - Tomoji Nakamura; Yoriko Mizushima; Young-Suk Kim; Ryuichi Sugie; Takayuki Ohba (3DIC, 2015)

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation. - Takayuki Ohba; Young-Suk Kim; Yoriko Mizushima; Nobuhide Maeda; Koji Fujimoto; Shoichi Kodama (IEICE Electron. Express, 2015)

Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias. - Chia-Hsuan Lee 003; Hsin-Chi Chang; Jui-Han Liu; Hiroyuki Ito; Young-Suk Kim; Kuan-Neng Chen; Takayuki Ohba (3DIC, 2019)

High Bandwidth Memory (HBM) and High Bandwidth NAND (HBN) with the Bumpless TSV Technology. - Koji Sakui; Takayuki Ohba (3DIC, 2019)

Three-dimensional Integration (3DI) with Bumpless Interconnects for Tera-scale Generation : High Speed, Low Power, and Ultra-small Operating Platform. - Koji Sakui; Takayuki Ohba (CICC, 2019)

Reliability of Wafer-Level Ultra-Thinning down to 3 µm using 20 nm-Node DRAMs. - Zhwen Chen; Young-Suk Kim; Tadashi Fukuda; Koji Sakui; Takayuki Ohba; Tatsuji Kobayashi; Takashi Obara (IRPS, 2021)

Low-ESL (<1 pH @ 8.5 GHz) Multi-Terminal Si Capacitor Embedded in 3D Functional Interposer for Power Delivery Network. - Kyosuke Kobinata; Tatsuya Funaki; Yoshiaki Satake; Hitoshi Matsuno; Seiji Hidaka; Shunsuke Abe; Hiroyuki Ito; Chih-Cheng Hsiao; Sheng Yi Li; Young-Suk Kim; Takayuki Ohba (VLSI Technology and Circuits, 2022)

Bumpless Build Cube (BBCube) 3D: Heterogeneous 3D Integration Using WoW and CoW to Provide TB/s Bandwidth with Lowest Bit Access Energy. - Norio Chujo; Koji Sakui; Shinji Sugatani; Hiroyuki Ryoson; Tomoji Nakamura; Takayuki Ohba (VLSI Technology and Circuits, 2023)

Face-Down and Heterogeneous Chip Bonding Technology on Waffle-Wafer for Bumpless Chip-an-Wafer (COW) Package. - Yoshiaki Satake; Tatsuya Funaki; Wataru Doi; Hajime Kato; Shogo Okita; Takayuki Ohba (3DIC, 2024)