18-GHz Clock Distribution Using a Coupled VCO Array. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEICE Trans. Electron., 2007)

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range. - Takayuki Shibasaki; Hirotaka Tamura; Kouichi Kanda; Hisakatsu Yamaguchi; Junji Ogawa; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2008)

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (ISSCC, 2009)

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS. - Kouichi Kanda; Hirotaka Tamura; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takayuki Shibasaki; Nestoras Tzartzanis; Anders Kristensson; Samir Parikh; Satoshi Ide; Yukito Tsunoda; et al. (IEEE J. Solid State Circuits, 2009)

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (CICC, 2010)

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS. - Nikola Nedovic; Anders Kristensson; Samir Parikh; Subodh M. Reddy; Scott McLeod; Nestoras Tzartzanis; Kouichi Kanda; Takuji Yamamoto; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Satoshi Ide; et al. (IEEE J. Solid State Circuits, 2010)

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order LC Oscillator Topology for Wide Locking Range. - Keita Takatsu; Hirotaka Tamura; Takuji Yamamoto; Yoshiyasu Doi; Kouichi Kanda; Takayuki Shibasaki; Tadahiro Kuroda (IEICE Trans. Electron., 2011)

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (ISSCC, 2013)

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process. - Yoshiyasu Doi; Takayuki Shibasaki; Takumi Danjo; Win Chaivipas; Takushi Hashida; Hiroki Miyaoka; Masanori Hoshino; Yoichi Koyanagi; Takuji Yamamoto; Sanroku Tsukamoto; Hirotaka Tamura (IEEE J. Solid State Circuits, 2013)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)

22.7 4×25.78Gb/s retimer ICs for optical links in 0.13μm SiGe BiCMOS. - Takayuki Shibasaki; Yukito Tsunoda; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS. - Yukito Tsunoda; Takayuki Shibasaki; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (ISSCC, 2015)

25.78-Gb/s VCSEL-based optical transceiver with retimer-embedded driver and receiver ICs. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Kazuhiro Tanaka; Tomohiro Ishihara; Hirotaka Tamura (OFC, 2015)

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. - Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Shigeaki Kawai; Tomoyuki Arai; Hirohito Higashi; et al. (ISSCC, 2016)

24 to 34-Gb/s ×4 multi-rate VCSEL-based optical transceiver with referenceless CDR. - Yukito Tsunoda; Takayuki Shibasaki; Hideki Oku; Jun Matsui; Takashi Shiraishi; Satoshi Ide; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (OFC, 2016)

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hisakatsu Yamaguchi; et al. (VLSI Circuits, 2016)

Session 6 overview: Ultra-high-speed wireline. - Simone Erba; Takayuki Shibasaki; Frank O'Mahony (ISSCC, 2017)

6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS. - Wahid Rahman; Danny Yoo; Joshua Liang; Ali Sheikholeslami; Hirotaka Tamura; Takayuki Shibasaki; Hisakatsu Yamaguchi (ISSCC, 2017)

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS. - Wahid Rahman; Danny Yoo; Joshua Liang; Ali Sheikholeslami; Hirotaka Tamura; Takayuki Shibasaki; Hisakatsu Yamaguchi (IEEE J. Solid State Circuits, 2017)

F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. - Bo Zhang; Frederic Gianesello; Simone Erba; Mounir Meghelli; Azita Emami; Takayuki Shibasaki (ISSCC, 2018)

A 30Gb/s 2x Half-Baud-Rate CDR. - Danny Yoo; Mohammad Bagherbeik; Wahid Rahman; Ali Sheikholeslami; Hirotaka Tamura; Takayuki Shibasaki (CICC, 2019)

A 36Gb/s Adaptive Baud-Rate CDR with CTLE and 1-Tap DFE in 28nm CMOS. - Danny Yoo; Mohammad Bagherbeik; Wahid Rahman; Ali Sheikholeslami; Hirotaka Tamura; Takayuki Shibasaki (ISSCC, 2019)

Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications. - Satoshi Matsubara; Motomu Takatsu; Toshiyuki Miyazawa; Takayuki Shibasaki; Yasuhiro Watanabe; Kazuya Takemoto; Hirotaka Tamura (ASP-DAC, 2020)