A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output. - Takashi Masuda; Hideyuki Suzuki; Hiroshi Iizuka; Akio Igarashi; Kaneyoshi Takeshita; Takayuki Mogi; Takayuki Shoji; Jeremy Chatwin; Iain Butler; Derek Mellor (ISSCC, 2007)