Unified Phase Compiler by Use of 3-D Representation Space. - Takefumi Miyoshi; Nobuhiko Sugino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Compiler for Architecture with Dynamic Reconfigurable Processing Unit by Use of Automatic Assignment Method of Sub-Programs Based on Their Quantitative Evaluation. - Takefumi Miyoshi; Nobuhiko Sugino (IEICE Trans. Inf. Syst., 2007)

Fine-grain compensation method with consideration of trade-offs between computation and data transfer for power consumption. - Takefumi Miyoshi; Nobuhiko Sugino (SIGARCH Comput. Archit. News, 2007)

A Study of an Infrastructure for Research and Development of Many-Core Processors. - Koh Uehara; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (PDCAT, 2009)

Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. - Kenichi Koizumi; Mary Inaba; Kei Hiraki; Yasuo Ishii; Takefumi Miyoshi; Kazuki Yoshizoe (ReConFig, 2009)

An Efficient Path Setup for a Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (ICNC, 2010)

CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. - Takefumi Miyoshi; Kenji Kise; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2010)

Pattern-Based Systematic Task Mapping for Many-Core Processors. - Shintaro Sano; Masahiro Sano; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

Smart Core System for Dependable Many-Core Processor with Multifunction Routers. - Shinya Takamaeda; Shimpei Sato; Takefumi Miyoshi; Kenji Kise (ICNC, 2010)

Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. - Qin Wang; Junichi Ohmura; Axida Shan; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2010)

OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Ping Qiu; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (IWIA, 2010)

A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine. - Takefumi Miyoshi; Hideyuki Kawashima; Yuta Terada; Tsutomu Yoshinaga (FPL, 2011)

CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. - Hidetsugu Irie; Takefumi Miyoshi; Goki Honjo; Kei Hiraki; Tsutomu Yoshinaga (ICNC, 2011)

An Implementation of Handshake Join on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (ICNC, 2011)

Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. - Junichi Ohmura; Akira Egashira; Shunji Satoh; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2011)

Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. - Junichi Ohmura; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2011)

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (Int. J. Netw. Comput., 2011)

FLAT: a GPU programming framework to provide embedded MPI. - Takefumi Miyoshi; Hidetsugu Irie; Keigo Shima; Hiroki Honda; Masaaki Kondo; Tsutomu Yoshinaga (GPGPU@ASPLOS, 2012)

Throttling Control for Bufferless Routing in On-chip Networks. - Yicheng Guan; Cisse Ahmadou Dit Adi; Takefumi Miyoshi; Michihiro Koibuchi; Hidetsugu Irie; Tsutomu Yoshinaga (MCSoC, 2012)

Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (MCSoC, 2012)

Using Cacheline Reuse Characteristics for Prefetcher Throttling. - Hidetsugu Irie; Takefumi Miyoshi; Goki Honjo; Kei Hiraki; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2012)

Design and Implementation of a Handshake Join Architecture on FPGA. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2012)

An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2013)

A fast handshake join implementation on FPGA with adaptive merging network. - Yasin Oge; Takefumi Miyoshi; Hideyuki Kawashima; Tsutomu Yoshinaga (SSDBM, 2013)

Hexa Cam: An FPGA-Based Multi-view Camera System. - Abraham Monrroy; Manato Hirabayashi; Shinpei Kato; Masato Edahiro; Takefumi Miyoshi; Satoshi Funada (CPSNA, 2015)

Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2015)

Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool. - Yuto Ishikawa; Keitaro Yanai; Keisuke Koike; Takefumi Miyoshi; Hironori Nakajo (HEART, 2017)

FPL Demo: A Flexible and Scalable Quantum-Classical Interface based on FPGAs. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Hidehisa Shiomi; Kazuhisa Ogawa; Yutaka Tabuchi; Makoto Negoro (FPL, 2022)

Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. - Ryohei Niwase; Hikaru Harasawa; Yoshiki Yamaguchi; Kaijie Wei; Hideharu Amano; Takefumi Miyoshi (ICFPT, 2023)

A state vector quantum simulator working on FPGAs with extensible SATA storage. - Kaijie Wei; Ryohei Niwase; Hideharu Amano; Yoshiki Yamaguchi; Takefumi Miyoshi (ICFPT, 2023)

A Fully Pipelined Architecture of Quantum-Classical Interface for Realizing Fault-Tolerant Quantum Computer. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Hidehisa Shiomi; Ryo Matsuda; Kazuhisa Ogawa; Yutaka Tabuchi; Makoto Negoro (QCE, 2023)

A Table Look-Up Based Quantum Simulation Accelerator on an FPGA. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ICFPT, 2024)

A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. - Takashi Imagawa; Ryo Kishida; Yuki Koyama 005; Kazutoshi Kobayashi; Takefumi Miyoshi (QCE, 2024)

Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. - Ryosuke Matsuo; Kazuhisa Ogawa; Hidehisa Shiorni; Makoto Negoro; Ryutaco Ohira; Takefumi Miyoshi; Michihiro Shintani; Hiromitsu Awano; Takashi Sato 001; Jun Shiomi (QCE, 2024)

A Microwave-Based QCCD Trapped-Ion Quantum Computer with Scalable Control System. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Toshi Sumida; Makoto Negoro; Atsushi Noguchi; Ryutaro Ohira (QCE, 2024)

Toward Scalable Heterogeneous Controller System for Various Quantum Computer by Using Multiple FPGAs. - Takefumi Miyoshi; Keisuke Koike; Shinichi Morisaka; Yuuya Sugita; Toshi Sumida; Yutaka Tabuchi; Makoto Negoro; Hidehisa Shiomi; Ippei Nakamura; Takafumi Tomita; Sylvain De Léséleuc; Atsushi Noguchi; et al. (ICCE, 2025)

A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. - Haruhiko Hasegawa; Masayuki Shimoda; Hiroki Nakahara; Takefumi Miyoshi (ISMVL, 2025)

Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages. - Kaijie Wei; Hideharu Amano; Ryohei Niwase; Yoshiki Yamaguchi; Takefumi Miyoshi (IEEE Trans. Computers, 2025)

Simulation environment for reconfigurable virtual accelerators using a field programmable gate array development environment. - Shunya Kawai; Eriko Maeda; Kazuki Yaguchi; Yasunori Osana; Takefumi Miyoshi; Hironori Nakajo (J. Supercomput., 2025)

Preliminary evaluation of SHAVER: sharing vector registers with an accelerator. - Tomoaki Tanaka; Michiya Kato; Yasunori Osana; Takefumi Miyoshi; Jubee Tada; Kiyofumi Tanaka; Hironori Nakajo (J. Supercomput., 2025)