A DRAM module generator with an expandable cell array scheme. - Hideki Takeuchi; Tomoaki Yabe; Shinji Miyano; Takehiko Hojo; Motohiro Enkaku; Masaaki Yamada; Masami Murakata (CICC, 1998)

Interface socket design methodology to generate embedded DRAM macros. - Ryo Haga; Tetsuya Kaneko; Atsushi Nakayama; Shinji Miyano; Hiroyuki Takenaka; Kenji Numata; Hiroyuki Koinuma; Takehiko Hojo; Akikuni Sato; Toshiyuki Kouchi; Kenichiro Mimoto; Masaaki Tazawa; et al. (CICC, 2001)

A 65nm low-power embedded DRAM with extended data-retention sleep mode. - Takeshi Nagai; Masaharu Wada; Hitoshi Iwai; Mariko Kaku; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano (ISSCC, 2006)

An 833MHz Pseudo-Two-Port Embedded DRAM for Graphics Applications. - Mariko Kaku; Hitoshi Iwai; Takeshi Nagai; Masaharu Wada; Atsushi Suzuki; Tomohisa Takai; Naoko Itoga; Takayuki Miyazaki; Takayuki Iwai; Hiroyuki Takenaka; Takehiko Hojo; Shinji Miyano; et al. (ISSCC, 2008)

13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. - Toshikazu Fukuda; Koji Kohara; Toshiaki Dozaka; Yasuhisa Takeyama; Tsuyoshi Midorikawa; Kenji Hashimoto; Ichiro Wakiyama; Shinji Miyano; Takehiko Hojo (ISSCC, 2014)