Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision Diagrams. - Masahiro Fujita; Yusuke Matsunaga; Takeo Kakuda (ICCAD, 1990)

Multi-Level Logic Minimization Across Latch Boundaries. - Yusuke Matsunaga; Masahiro Fujita; Takeo Kakuda (ICCAD, 1990)