Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. - Tadashi Shibata; Koji Kotani; Takeo Yamashita; Hiroshi Ishii 005; Hideo Kosaka; Tadahiro Ohmi (NIPS, 1993)

Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. - Tadashi Shibata; Tsutomu Nakai; Tatsuo Morimoto; Ryu Kaihara; Takeo Yamashita; Tadahiro Ohmi (NIPS, 1995)

Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. - Tamotsu Miyake; Takeo Yamashita; Norikatsu Asari; Hideki Sekisaka; Tom Sakai; Kazuhiro Matsuura; Atsushi Wakahara; Hideyuki Takahashi; Tom Hiyama; Kazuhisa Miyamoto; Kazutaka Mori (CICC, 2001)

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. - Takashi Kawamoto; Takayasu Norimatsu; Kenji Kogo; Fumio Yuki; Norio Nakajima; Masatoshi Tsuge; Tatsunori Usugi; Tomofumi Hokari; Hideki Koba; Takemasa Komori; Junya Nasu; Tsuneo Kawamata; et al. (ISSCC, 2015)

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. - Takayasu Norimatsu; Takashi Kawamoto; Kenji Kogo; Naohiro Kohmu; Fumio Yuki; Norio Nakajima; Takashi Muto; Junya Nasu; Takemasa Komori; Hideki Koba; Tatsunori Usugi; Tomofumi Hokari; et al. (ISSCC, 2016)