High-speed wide-locking range VCO with frequency calibration. - Takeo Yasuda (ISCAS, 2000)

A dynamically phase adjusting PLL with a variable delay. - Takeo Yasuda; Hiroaki Fujita; Hidetoshi Onodera (ASP-DAC, 2001)

A power-on reset pulse generator for low voltage applications. - Takeo Yasuda; Masaaki Yamamoto; Takafumi Nishi (ISCAS (4), 2001)

An On-Chip Power-on Reset Circuit for Low Voltage Technology. - Takeo Yasuda; Masaaki Yamamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A low power CMOS circuit with Variable Souce Scheme (VSCMOS). - Takeo Yasuda; Kohji Hosokawa (ASP-DAC, 2003)

On-chip temperature sensor with high tolerance for process and temperature variation. - Takeo Yasuda (ISCAS (2), 2005)

Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers. - Atsuya Okazaki; Pritish Narayanan; Stefano Ambrogio; Kohji Hosokawa; Hsinyu Tsai; Akiyo Nomura; Takeo Yasuda; Charles Mackin; Alexander M. Friz; Masatoshi Ishii; Yasuteru Kohda; Katie Spoon; et al. (ISCAS, 2022)

Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited). - Hsinyu Tsai; Pritish Narayanan; Shubham Jain; Stefano Ambrogio; Kohji Hosokawa; Masatoshi Ishii; Charles Mackin; Ching-Tzu Chen; Atsuya Okazaki; Akiyo Nomura; Irem Boybat; Ramachandran Muralidhar; et al. (ISCAS, 2023)

Phase Change Memory-based Hardware Accelerators for Deep Neural Networks (invited). - Geoffrey W. Burr; Pritish Narayanan; Stefano Ambrogio; Atsuya Okazaki; Hsinyu Tsai; Kohji Hosokawa; Charles Mackin; Akiyo Nomura; Takeo Yasuda; J. Demarest; Kevin Brew; Victor Chan; et al. (VLSI Technology and Circuits, 2023)

An analog-AI chip for energy-efficient speech recognition and transcription. - Stefano Ambrogio; Pritish Narayanan; Atsuya Okazaki; Andrea Fasoli; Charles Mackin; Kohji Hosokawa; Akiyo Nomura; Takeo Yasuda; An Chen 002; Alexander M. Friz; Masatoshi Ishii; Jose Luquin; et al. (Nat., 2023)