A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. - Masaki Tsukude; Shigehiro Kuge; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 1997)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs. - Takeshi Fujino; Akira Yamazaki; Yasuhiko Taito; Mitsuya Kinoshita; Fukashi Morishita; Teruhiko Amano; Masaru Haraguchi; Makoto Hatakenaka; Atsushi Amo; Atsushi Hachisuka; Kazutami Arimoto; Hideyuki Ozaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. - Yasuhiko Taito; Tetsushi Tanizaki; Mitsuya Kinoshita; Futoshi Igaue; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 2003)

Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. - Akihiro Nakamura; Masahide Kawaharazaki; Masaya Yoshikawa; Takeshi Fujino (CICC, 2007)

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. - Akihiro Nakamura; Masahide Kawarasaki; Kouta Ishibashi; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Electron., 2008)

Placement Tool Dedicated for a Via-programmable Logic Device VPEX. - Masaya Yoshikawa; Yuichi Kokusyo; Takeshi Fujino (CAINE, 2010)

Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. - Katsuhiko Iwai; Mitsuru Shiozaki; Anh-Tuan Hoang; Kenji Kojima; Takeshi Fujino (HOST, 2011)

The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. - Kota Furuhashi; Mitsuru Shiozaki; Akitaka Fukushima; Takahiko Murayama; Takeshi Fujino (ISCAS, 2011)

Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. - Masaya Yoshikawa; Takeshi Fujino (Int. J. Comput. Their Appl., 2011)

Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. - Hiroki Ito; Mitsuru Shiozaki; Anh-Tuan Hoang; Takeshi Fujino (DSD, 2012)

Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. - Anh-Tuan Hoang; Takeshi Fujino (FPGA, 2012)

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. - Ryohei Hori; Tatsuya Kitamori; Taisuke Ueoka; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. - Ryohei Hori; Taisuke Ueoka; Taku Otani; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. - Mitsuru Shiozaki; Kota Furuhashi; Takahiko Murayama; Akitaka Fukushima; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Electron., 2012)

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). - Anh-Tuan Hoang; Takeshi Fujino (FPGA, 2013)

A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. - Masato Taniguchi; Mitsuru Shiozaki; Hiroshi Kubo; Takeshi Fujino (GCCE, 2013)

Hierarchical image-scrambling method with scramble-level controllability for privacy protection. - Toshiya Honda; Yuma Murakami; Yuki Yanagihara; Takeshi Kumaki; Takeshi Fujino (MWSCAS, 2013)

Cipher-destroying and secret-key-emitting hardware Trojan against AES core. - Takeshi Kumaki; Masaya Yoshikawa; Takeshi Fujino (MWSCAS, 2013)

Development of effective information-hiding method for embedded systems. - Kei Nakao; Kohei Hozumi; Takeshi Kumaki; Takeshi Ogura; Takeshi Fujino (MWSCAS, 2013)

The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. - Ryohei Hori; Taisuke Ueoka; Taku Otani; Masaya Yoshikawa; Takeshi Fujino (VLSI-DAT, 2013)

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. - Takeshi Kumaki; Takeshi Fujino; Tetsushi Koide (APCCAS, 2014)

Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. - Tsunato Nakai; Megumi Shibatani; Mitsuru Shiozaki; Takaya Kubota; Takeshi Fujino (ISCAS, 2014)

Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection. - Yuki Yanagihara; Toshiya Honda; Takeshi Kumaki; Takeshi Fujino (ISCAS, 2014)

Diffusion Programmable Device : The device to prevent reverse engineering. - Mitsuru Shiozaki; Ryohei Hori; Takeshi Fujino (IACR Cryptol. ePrint Arch., 2014)

Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. - Takeshi Kumaki; Kei Nakao; Kohei Hozumi; Takeshi Ogura; Takeshi Fujino (IEICE Trans. Inf. Syst., 2014)

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. - Koichi Shimizu; Daisuke Suzuki; Toyohiro Tsurumaru; Takeshi Sugawara 001; Mitsuru Shiozaki; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. - Mitsuru Shiozaki; Kousuke Ogawa; Kota Furuhashi; Takahiko Murayama; Masaya Yoshikawa; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

On measurable side-channel leaks inside ASIC design primitives. - Takeshi Sugawara 001; Daisuke Suzuki; Minoru Saeki; Mitsuru Shiozaki; Takeshi Fujino (J. Cryptogr. Eng., 2014)

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. - Anh-Tuan Hoang; Takeshi Fujino (ACM Trans. Reconfigurable Technol. Syst., 2014)

Development of LED illumination-based spy photo-prevention system. - Kyosuke Kageyama; Kohei Sugiyama; Takeshi Kumaki; Takeshi Fujino (GCCE, 2015)

Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. - Mitsuru Shiozaki; Takaya Kubota; Tsunato Nakai; Akihiro Takeuchi; Takashi Nishimura; Takeshi Fujino (ISCAS, 2015)

Proposal of LED-based Peeping Prevention System. - Kyosuke Kageyama; Kohei Sugiyama; Takeshi Kumaki; Takeshi Fujino (MWSCAS, 2015)

Reversing stealthy dopant-level circuits. - Takeshi Sugawara 001; Daisuke Suzuki; Ryoichi Fujii; Shigeaki Tawa; Ryohei Hori; Mitsuru Shiozaki; Takeshi Fujino (J. Cryptogr. Eng., 2015)

Malicious CAN-message attack against advanced driving assistant system. - Mitsuru Shiozaki; Takaya Kubota; Masashi Nakano; Yuuki Nakazawa; Takeshi Fujino (HOST, 2017)

Tamper-resistant cryptographic hardware. - Takeshi Fujino; Takaya Kubota; Mitsuru Shiozaki (IEICE Electron. Express, 2017)

Hierarchical-Masked Image Filtering for Privacy-Protection. - Takeshi Kumaki; Takeshi Fujino (IEICE Trans. Inf. Syst., 2017)

A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. - Shunsuke Okura; Ryota Ishiki; Masayoshi Shirahata; Takaya Kubota; Mitsuru Shiozaki; Kenichiro Ishikawa; Isao Takayanagi; Takeshi Fujino (ISPACS, 2018)

Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. - Mitsuru Shiozaki; Takeshi Fujino (ASHES@CCS, 2019)

Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. - Kota Yoshida; Takaya Kubota; Mitsuru Shiozaki; Takeshi Fujino (FCCM, 2019)

Exploring Effect of Residual Electric Charges on Cryptographic Circuits. - Mitsuru Shiozaki; Takeshi Sugawara 001; Takeshi Fujino (ASHES@CCS, 2020)

Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks. - Kota Yoshida; Takeshi Fujino (AISec@CCS, 2020)

Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. - Mitsuru Shiozaki; Yohei Hori; Tatsuya Oyama; Masayoshi Shirahata; Takeshi Fujino (ISCAS, 2020)

Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. - Kota Yoshida; Takaya Kubota; Shunsuke Okura; Mitsuru Shiozaki; Takeshi Fujino (ISCAS, 2020)

Entropy Estimation of Physically Unclonable Functions. - Mitsuru Shiozaki; Yohei Hori; Takeshi Fujino (IACR Cryptol. ePrint Arch., 2020)

Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (ACNS Workshops, 2021)

Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment. - Kota Yoshida; Takeshi Fujino (ACNS Workshops, 2021)

Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES. - Yuta Fukuda; Kota Yoshida; Hisashi Hashimoto; Takeshi Fujino (AsianHOST, 2021)

Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code. - Kota Yoshida; Kuniyasu Suzaki; Takeshi Fujino (HASP@MICRO, 2021)

Modeling attacks against device authentication using CMOS image sensor PUF. - Hiroshi Yamada; Shunsuke Okura; Masayoshi Shirahata; Takeshi Fujino (IEICE Electron. Express, 2021)

Adversarial Black-Box Attacks with Timing Side-Channel Leakage. - Tsunato Nakai; Daisuke Suzuki; Fumio Omatsu; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. - Kota Yoshida; Mitsuru Shiozaki; Shunsuke Okura; Takaya Kubota; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. - Mitsuru Shiozaki; Takeshi Fujino (J. Cryptogr. Eng., 2021)

Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. - Shunsuke Okura; Masanori Aoki; Tatsuya Oyama; Masayoshi Shirahata; Takeshi Fujino; Kenichiro Ishikawa; Isao Takayanagi (Sensors, 2021)

Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021)

Deep learning side-channel attack against hardware implementations of AES. - Takaya Kubota; Kota Yoshida; Mitsuru Shiozaki; Takeshi Fujino (Microprocess. Microsystems, 2021)

Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. - Tsunato Nakai; Daisuke Suzuki; Takeshi Fujino (ACNS Workshops, 2022)

Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Kota Yoshida; Shunsuke Okura; Takeshi Fujino (AsianHOST, 2022)

Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64. - Madoka Sakou; Kunihiro Kuroda; Yuta Fukuda; Kota Yoshida; Takeshi Fujino (ATAIT, 2022)

Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication. - Seiya Shimada; Kunihiro Kuroda; Yuta Fukuda; Kota Yoshida; Takeshi Fujino (ATAIT, 2022)

Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller. - Yuta Fukuda; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. - Tatsuya Oyama; Shunsuke Okura; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM. - Kota Yoshida; Masaya Hojo; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

Evaluation of Membership Inference Attack Against Federated Learning With Differential Privacy on Edge Devices. - Rei Ueda; Tsunato Nakai; Kota Yoshida; Takeshi Fujino (GCCE, 2023)

Multispectral Pedestrian Detection with Visible and Far-infrared Images Under Drifting Ambient Light and Temperature. - Masato Okuda; Kota Yoshida; Takeshi Fujino (SENSORS, 2023)

Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples. - Yuta Fukuda; Kota Yoshida; Takeshi Fujino (IEEE Access, 2023)

Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Shunsuke Okura; Kota Yoshida; Takeshi Fujino (Sensors, 2023)

Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure. - Yuta Fukuda; Kota Yoshida; Hisashi Hashimoto; Kunihiro Kuroda; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. - Mitsuru Shiozaki; Takeshi Sugawara 001; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM. - Kunihiro Kuroda; Yuta Fukuda; Kota Yoshida; Takeshi Fujino (J. Cryptogr. Eng., 2023)

Incorporating Cluster Analysis of Feature Vectors for Non-profiled Deep-learning-Based Side-Channel Attacks. - Yuta Fukuda; Kota Yoshida; Takeshi Fujino (ACNS Workshops (1), 2024)

FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. - Tatsuya Oyama; Mika Sakai; Yohei Hori; Toshihiro Katashita; Takeshi Fujino (ACNS Workshops (1), 2024)

Model Extraction Attack Without Natural Images. - Kota Yoshida; Takeshi Fujino (ACNS Workshops (2), 2024)

Evaluation of Accuracy and Security on Deep Learning Model by Utilizing K-Anonymization With Attribute Selection for Reducing Computational Cost. - Rei Ueda; Kota Yoshida; Takeshi Fujino (GCCE, 2024)

Defense Method Against Adversarial Example Attacks using Thermal Noise of a CMOS Image Sensor. - Yuki Rogi; Kota Yoshida; Tatsuya Oyama; Takeshi Fujino; Shunsuke Okura (IEEE SENSORS, 2024)

Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. - Tatsuya Oyama; Kota Yoshida; Shunsuke Okura; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

SEDMA: Self-Distillation with Model Aggregation for Membership Privacy. - Tsunato Nakai; Ye Wang; Kota Yoshida; Takeshi Fujino (Proc. Priv. Enhancing Technol., 2024)

Data Poisoning Attack against Neural Network-Based On-Device Learning Anomaly Detector by Physical Attacks on Sensors. - Takahito Ino; Kota Yoshida; Hiroki Matsutani; Takeshi Fujino (Sensors, 2024)

Multi-Bit DDLA: Non-Profiled Deep Learning Side-Channel Attacks Using Multi-Bit Label against Hardware-Implemented AES. - Yuta Fukuda; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

CA-SCA: Non-Profiled Deep Learning-Based Side-Channel Attacks by Using Cluster Analysis. - Yuta Fukuda; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)

Mitigation of Membership Inference Attack by Knowledge Distillation on Federated Learning. - Rei Ueda; Tsunato Nakai; Kota Yoshida; Takeshi Fujino (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2025)