An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

A 45-ns 16-Mbit DRAM with triple-well structure. - Syuso Fujii; Masaki Ogihara; Mitsuru Shimizu; Munehiro Yoshida; Kenji Numata; Takahiko Hara; Shigeyoshi Watanabe; Shizuo Sawada; Tomohisa Mizuno; Junpei Kumagai; Susumu Yoshikawa; Sejii Kaki; et al. (IEEE J. Solid State Circuits, 1989)

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. - Tadato Yamagata; Masaaki Mihara; Takeshi Hamamoto; Yasumitsu Murai; Toshifumi Kobayashi; Michihiro Yamada; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1992)

An experimental DRAM with a NAND-structured cell. - Takehiro Hasegawa; Daisaburo Takashima; Ryu Ogiwara; Masako Ohta; Shinichiro Shiratake; Takeshi Hamamoto; Takashi Yamada; Masami Aoki; Shigeru Ishibashi; Yukihito Oowaki; Shigeyoshi Watanabe; Fujio Masuoka (IEEE J. Solid State Circuits, 1993)

Cell-plate-line/bit-line complementary sensing (CBCS) architecture for ultra low-power DRAMs. - Takeshi Hamamoto; Yoshikazu Maroaka; Mikio Asakura; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1996)

400-MHz random column operating SDRAM techniques with self-skew compensation. - Takeshi Hamamoto; Masaki Tsukude; Kazutami Arimoto; Yasuhiro Konishi; Takayuki Miyamoto; Hideyuki Ozaki; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A precharged-capacitor-assisted sensing (PCAS) scheme with novel level controllers for low-power DRAMs. - Takashi Kono; Takeshi Hamamoto; Katsuyoshi Mitsui; Yasuhiro Konishi; Tsutomu Yoshihara; Hideyuki Ozaki (IEEE J. Solid State Circuits, 2000)

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica. - Shigehiro Kuge; Tetsuo Kato; Kiyohiro Furutani; Shigeru Kikuda; Katsuyoshi Mitsui; Takeshi Hamamoto; Jun Setogawa; Kei Hamade; Yuichiro Komiya; Satoshi Kawasaki; Takashi Kono; Teruhiko Amano; et al. (IEEE J. Solid State Circuits, 2000)

Semi-automatic Compilation of Bilingual Lexicon Entries from Cross-Lingually Relevant News Articles on WWW News Sites. - Takehito Utsuro; Takashi Horiuchi; Yasunobu Chiba; Takeshi Hamamoto (AMTA, 2002)

Effect of Cross-Language IR in Bilingual Lexicon Acquisition from Comparable Corpora. - Takehito Utsuro; Takashi Horiuchi; Takeshi Hamamoto; Kohei Hino; Takeaki Nakayama (EACL, 2003)

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM. - Takeshi Hamamoto; Kiyohiro Furutani; Takashi Kubo; Satoshi Kawasaki; Hironori Iga; Takashi Kono; Yasuhiro Konishi; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2004)

Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories. - Kiyohiro Furutani; Takeshi Hamamoto; Takeo Miki; Masaya Nakano; Takashi Kono; Shigeru Kikuda; Yasuhiro Konishi; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

Design of a 128-mb SOI DRAM using the floating body cell (FBC). - Takashi Ohsawa; Katsuyuki Fujita; Kosuke Hatsuda; Tomoki Higashi; Tomoaki Shino; Yoshihiro Minami; Hiroomi Nakajima; Mutsuo Morikado; Kazumi Inoh; Takeshi Hamamoto; Shigeyoshi Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2006)

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (ISSCC, 2009)

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (ISSCC, 2010)

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. - Hidehiro Shiga; Daisaburo Takashima; Shinichiro Shiratake; Katsuhiko Hoya; Tadashi Miyakawa; Ryu Ogiwara; Ryo Fukuda; Ryosuke Takizawa; Kosuke Hatsuda; Fumiyoshi Matsuoka; Yasushi Nagadomi; Daisuke Hashimoto; et al. (IEEE J. Solid State Circuits, 2010)

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs. - Daisaburo Takashima; Hidehiro Shiga; Daisuke Hashimoto; Tadashi Miyakawa; Shinichiro Shiratake; Katsuhiko Hoya; Ryu Ogiwara; Ryosuke Takizawa; Ryosuke Doumae; Ryo Fukuda; Yohji Watanabe; Shuso Fujii; et al. (IEEE J. Solid State Circuits, 2011)

Evaluation methodology for current collapse phenomenon of GaN HEMTs. - Toru Sugiyama; Kohei Oasa; Yasunobu Saito; Akira Yoshioka; Takuo Kikuchi; Aya Shindome; Tatsuya Ohguro; Takeshi Hamamoto (IRPS, 2018)